Figure 8 shows a simple combinational logic circuit. The numbers associated with

Question

Figure 8 shows a simple combinational logic circuit. The numbers associated with each gate are the propagation delays. Below is a segment of Verilog behavioral code that describes the circuit, with a process (always blocks), corresponding to each gate.

{{{{module CombCircuit( input wire x,y,z, output reg w); reg a,b; always @(*) a = #3 y & z; always @(*) b = #1 ~x; always @(*) #4 w = a | b; endmodule // CombCircuit module CombCircuit_tb; reg x,y,z; wire w; CombCircuit CC(x,y,z,w); initial begin {x,y,z} = 3’b011; $display("$time=%d,x=%b,y=%b,z=%b,w=%b", $time,x,y,z,w); #8 {x,y,z} = 3’b100; wait(~w); $display("$time=%d,x=%b,y=%b,z=%b,w=%b", $time,x,y,z,w); end // initial begin endmodule // CombCiruit_tb }}}

(a) Write the ouput of a Verilog simulator would be after simulating the module CombCircuit tb.

(b) Does the Verilog module ’CombCircuit’ correctly model the propagation delay of the combinational logic in Figure 8? Explain your answer.

(c) If your answer to question (b) is negative, then identify what changes you would make and write the output of a Verilog simulator would be for the modified description.

Explanation / Answer

module addbit ( 2 a , // first input 3 b , // Second input 4 ci , // Carry input 5 sum , // sum output 6 co // carry output 7 ); 8 //Input declaration 9 input a; 10 input b; 11 input ci; 12 //Ouput declaration 13 output sum; 14 output co; 15 //Port Data types 16 wire a; 17 wire b; 18 wire ci; 19 wire sum; 20 wire co; 21 //Code starts here 22 assign {co,sum} = a + b + ci; 23 24 endmodule // End of Module addbit

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