Figure 5.16 shows that step 3 of a conditional branch instruction may result in
ID: 3685265 • Letter: F
Question
Figure 5.16 shows that step 3 of a conditional branch instruction may result in a new value being loaded into the PC. In pipelined processors, it is desirable to determine the outcome of a conditional branch as early as possible in the execution sequence.
a) What hardware changes would be needed to make it possible to move the action in step 3 to step 2? Examine all the actions involved in these two steps and show which actions can be carried out in parallel and which must be completed sequentially.
b) Perform a worst case delay analysis of the updated processor in part a). Consider the delays provided in Problem 3.
i. Determine the minimum time needed for each of the stage.
ii. Ignoring all other delays, what is the minimum clock period that can be used for this processor?
Step Action Memory address [PCI, Read memory, IR Memory data, PC [PC] + 4 Decode instruction, RA [RS, RBR6] Compare [RA] to [RB], If [RA] = [RB], then PC [PC] + Branch offset 4 No action 5 No action Sequence of actions needed to fetch and execute the instruction: Branch_if_IR51-IR6] LOOP. Figure 5.16Explanation / Answer
program counter (PC) holds the address or location of the instruction being executed currently Hence PC = address of current instruction being executed step1: load contents of PC into the memory address read the memory put the memory data into IR ( IR = Instruction Register) increment PC by 4 step2: decode or decipher the instructions Reg 5 to reg A, reg 6 to reg B step 3 loads a new value in to the program counter (PC) this step 3 is a conditional branch instruction assuming RA = Register A and RB = register(reg) B as it compares RA and RB, if they are equal, then PC = PC + Offset address of the Branch instruction or where it is supposed to jump to if ( reg A == reg B) then PC += Branch Offset the following actions can be carried out in parallel: the following actions cannot be carried out in parallel and needs sequential execution: Pillars of delay analysis torus and router structure radix , nodes or vertices hardware change that can reduce the delay of course adding extra Random Access Memory (RAM) will reduce the delay but we will explore better options Hardware upgrade includes adding extra RAMs Better clock speed processors like Intel clock pulse or clock period is the single pulse that goes up and down like a digitized sine wave
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