Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a b

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Question

Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2 . Then there is a recharge time, lasting from t2 to t3, during which DRAM chips will have to recharge before the processor can access them again.

The questions are:

a. Assume that the access time is 60 ns and the recharge time is 40 ns. What is the memory cycle time?

What is the maximum data rate this DRAM can sustain, assuming a 1-bit output?

b. Constructing a 32-bit wide memory system using these chips yields what data transfer rate?

Explanation / Answer

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a.Memory cycle time=60+40=100ns

maximum data rate:

for 1 bit it takes 100ns

or for 100ns it finds 1bit

or for 100 x 10^-9s it finds 1 bit

for 1s it finds 1/(100 x 10^-9)bits

=>maximum data rate=10^7 bits/sec

b.For a 32 bit wide memory system the data transfer rate = 32 x 10^7 bits/sec

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Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a b

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