Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a b

Question

Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2 . Then there is a recharge time, lasting from t2 to t3, during which DRAM chips will have to recharge before the processor can access them again.

a. Assume that the access time is 60 ns and the recharge time is 40 ns. What is the memory cycle time?

What is the maximum data rate this DRAM can sustain, assuming a 1-bit output?

b. Constructing a 32-bit wide memory system using these chips yields what data transfer rate?

Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2 . Then there is a recharge time, lasting from t2 to t3, during which DRAM chips will have to recharge before the processor can access them again. a. Assume that the access time is 60 ns and the recharge time is 40 ns. What is the memory cycle time? What is the maximum data rate this DRAM can sustain, assuming a 1-bit output? b. Constructing a 32-bit wide memory system using these chips yields what data transfer rate?

Explanation / Answer

If the access time is 60ns and the recharge time is 40ns, then the cycle time would be 100ns, since the system needs to perform the access and then recharge prior to next access. This gives a rate of 1s / 100ns = 10,000,000 accesses/sec * 1 bit/access = 10Mbits/sec data transfer rate. b) If you have a 32-bit wide memory bank made of these chips, you get 10Mbits/sec/chip * 32 chips = 320Mbit/sec data transfer rate.

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