Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a b

Question

Figure 5.16 shows a simplified timing diagram for a DRAM read operation over a bus. The access time is considered to last from t1 to t2 . Then there is a recharge time, lasting from t2 to t3, during which DRAM chips will have to recharge before the processor can access them again.

The questions are:

a. Assume that the access time is 80 ns and the recharge time is 20 ns. What is the memory cycle time?

What is the maximum data rate this DRAM can sustain, assuming a 1-bit output?

b. Constructing a 16-bit wide memory system using these chips yields what data transfer rate?

Explanation / Answer

a.) Memory cycle time = Minimum time delay required between two successive operations

=> Memory cycle time = Access time + Recharge time = (80 + 20)ns = 100ns

Data rate = Output data/ Time taken for the output data to get obtained

=> Data rate = 1 bit / Memory cycle time = 1 bit/(100 * 10^-9)s = 10^7 bits/second = 10 megabits/second

b.) Data transfer rate = 16 bits / Memory cycle time = 16 bits/(100*10^-9)s = (16*10^7) bits/second

=160 megabits/second

Related Questions

Navigate

• Browse (All)
• Browse F
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.