18.What technique allows you bypass the CPU when transferring data from main mem
ID: 3852636 • Letter: 1
Question
18.What technique allows you bypass the CPU when transferring data from main memory to an I/O device.
19. The line size of a cache chunk is usually between ????? and ?????? bytes
20. The LMC instruction 392 performs what type of function?
21.If you have a true color display using 8 bits for the intensity of each primary color. How many colors can you create for the display
22. Name the fastest type of cache memory in a computer architecture is ????? 23. In a RISC architecture all the opcodes are of the same ???????
24. In a SMP system it is important to maintain cache coherency since multiple processors are accessing a common memory. Listening for cache events on the memory bus shared by multiple processors is referred to as ?????????????
24. When one instruction can prematurely access data from a register that is being acted upon by a previous instruction, this creates a pipeline event known as a data ?????????????.
25. A ?????????????? cache delays writing the changes to RAM until absolutely necessary
Explanation / Answer
18. DMA
Stands for "Direct Memory Access." DMA is a method of transferring data from the computer's RAM to another part of the computer without processing it using the CPU.
19. 32, 64 and 128 bytes
The size of these chunks is called the cache line size. Common cache line sizes are 32, 64 and 128 bytes.
22. L1 Cache
The cache closest to CPU is always faster but generally costs more and stores less data then other level of cache.
23.Uniform instruction format
24.Symmetric Multi-Processing
In a SMP system there are multiple processors that share other all other system resources (memory, disk, etc).
25. Results
Instructions flow through the pipeline in one direction, ("up") and the answers computed by previous instructions, called "results," flow in the other direction, ("down").
26.write-back cache
write-back cache delays writing the changes to RAM until absolutely necessary.
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