A particular (fictional) CPU has the following internal units and timings. 1. IF

Question

A particular (fictional) CPU has the following internal units and timings. 1. IFD: Instruction fetch + decode: 160 ps 2. RR: Register read: 80 ps 3. ALU: 240 ps 4. MA: memory access: 160 ps (assuming cache) 5. RW: register write: 80 ps There are 5 basic instruction types: 1. LOAD: IFD + RR + ALU + MA + RW: 720 ps 2. STORE: IFD + RR + ALU + MA: 640 ps 3. ARITHMETIC: IFD + RR + ALU + RW: 560 4. BRANCH: IFD + RR + ALU: 480 ps 5. MEMOP: IFD + RR + MA + ALU + MA: 800 ps A. What is the frequency of this machine without a pipeline? B. What is the frequency for a pipelined version of this CPU? C. What is the datapath for the pipeline - that is, what functional units

Explanation / Answer

In case of Pipelined approach, maximum amount of time consumed by CPU for each unit of task is 240ps.So considering that all task are completed in 1 clock cycle only, each clock cycle cannot be less than 240ps (so taht we can accomodate all cases). So if the time period is at least 240ps,so cpu frequency would be at most 4.16Mhz

In the other case where no pipelines are being used, each instruction will be executed without parrallism. So looking into the table, we can say that without the use of pipeline, the clock period should be atleast be 800ms, so the clock frequency can be atmost be 1.25MHz.

Basic five-stage pipeline are IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, and WB = Register write back.

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