1. The following code adds integers in two arrays (whose address is in $s0 and $
ID: 3707936 • Letter: 1
Question
1. The following code adds integers in two arrays (whose address is in $s0 and $s1) and stores the results back into the first array. $s2 is initialized to 0. Ss3 is 100 I2: I3: I 4: I5: I6: I7: I8: I9: add SW addi addi addi bne St0, ($s0) Stl, ($s1) Sto, $to, St1 St0, ($s0) $s0, $s0, 4 $s1, $s1, 4 Ss2, $s2, 1 Ss2, $s3, I1 Assume a MIPS processor with a 5-stage pipeline. Branches are not delayed For each of the following implementations of MIPS, show the pipeline diagram from the lF stage of 11 to the IF stage of 11 in the next iteration You are not required to list but you should know which forwarding path is used and when 1. This implementation does not have any forwarding paths. The conditional branch is resolved in the MEM stage and the correct instruction is fetched in the WB stage of the branch instruction. The pipeline stalls before the conditional branch is resolved 1. This implementation has all the forwarding paths needed for better performance. The conditional branch is resolved in the ID stage. The implementation also use a static branch predictor that predicts not-taken. If the prediction is correct, there is no performance penalty on branchesExplanation / Answer
ANSWER:
1) Implementation of 5 stage pipeline without forwarding
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
I1 IF ID EX MEM WB
I2 IF ID EX MEM WB
I3 IF Stall Stall ID EX MEM WB
I4 IF Stall Stall ID EX MEM WB
I5 IF Stall Stall ID EX MEM WB
I6 IF ID Ex MEM WB
I7 IF ID EX MEM WB
I8 IF ID EX MEM WB
I9 Stall Stall Stall IF ID EX MEM WB
Explanation:-
In this implementation no forwarding happens after execution cycle.
So third instruction need registers that are now using first and second instructions,so they stall the ID cycle.
This will happen next two instructions also.
Last branch taken or not will find out after MEM cycle,So first three cycles of next instruction stalled.
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2) Implementation of 5 stage pipeline with data forwarding and branch prediction
Instructions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I1 IF ID EX MEM WB
I2 IF ID EX MEM WB
I3 IF stall ID EX MEM WB
I4 IF ID EX MEM WB
I5 IF ID Stall EX MEM WB
I6 IF ID EX MEM WB
I7 IF ID EX MEM WB
I8 IF Stall ID EX MEM WB
I9 IF idl idl idl Idl
I1 IF ID EX MEM WB
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