You as a digital designer are asked to propose arithmetic architecture that will

Question

You as a digital designer are asked to propose arithmetic architecture that will produce 32-bit result the most power efficient way with minimum are area overhead. The 32 bits represents R, G, B and Grayscale colors, each 8 bit wide. You have a choice to design 4 arithmetic circuits computing R, G, B, GS in parallel (4 times 8) or in series using one arithmetic circuit multiplexed (1 times 8 times 4) or 2 times 16 or 1 times 32. Describe what choice of adder would you select and provide the justification for your choice.

Explanation / Answer

I Can go ripple adder which can be operated by using multiplexers.Because it consumes less area

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