A particular CMOS gate operates at a particular switching frequency f, employs a

Question

A particular CMOS gate operates at a particular switching frequency f, employs a particular load capacitance C, and switches through a particular voltage V. Suppose that the switching frequency is decreased to 90 percent of its current value – that is, fnew = 0.9 * fold.

If the voltage remains the same, by what factor could the load capacitance be changed so that the gate consumes the same amount of dynamic power as it did before the switching frequency was changed?

If the load capacitance remains the same, by what factor could the voltage be changed so that the gate consumes the same amount of dynamic power as it did before the switching frequency was changed?

Explanation / Answer

Given,

Switching frequency f, Supply Voltage V, Load capacitance C,

Dynamic Power is the power consumption across load capacitance during switching which is defined as eq.(1)

Dynamic power (Pd) = Energy / transition * Transition rate

Pd = C * V2 * Nsw * f        .....(1)

where Nsw is number of bits switching; for single bit switching Nsw in eq(1) is 1.

So, Pd=C * V2 * f

After switching frequency reduces to 90% of f,

Pd=C * V2 * 0.9f

CASE:1

Considering supply voltage(V) as constant, then for same dynamic power as before switching, new load capacitance is given as,

Cnew * V2 * 0.9f = C* V2 * f

Cnew = C/0.9

Cnew = 1.11 * C

New load capacitance(Cnew) will be 1.11 times of initial load capacitance(C).

CASE:2

Considering load capacitance(C) as constant, then for same dynamic power as before switching, new supply voltage(Vnew) is given as,

C * Vnew2 * 0.9f = C* V2 * f

Vnew2 = V2 / 0.9

Vnew =1.054 * V

New supply voltage(Vnew) will be 1.054 times of initial supply voltage(V).

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