Figure 3(a) shows the waveforms to be generated using a VHDL test bench to simul

Q: Figure 3(a) shows the waveforms to be generated using a VHDL test bench to simul

a). To generate the required EN signal: EN: process begin Wait for 8ns; EN

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Question

Figure 3(a) shows the waveforms to be generated using a VHDL test bench to simulate the counter described by its entity in Figure 3(b). Entity Counter is port (CLK, RESET, EN: in std_logic; O: out std_logic_vector (0 to 3)); end Counter; sing the wait statement, write two processes to generate: The EN signal shown in Fig 3(a); and The RESET signal shown in Fig 3(a). Write the statement that can be used within a VHDL test bench that checks that the output O is equal to 3 and reports an error if it is not.

Explanation / Answer

a). To generate the required EN signal:

EN: process

begin

Wait for 8ns;

EN<='1';

end process EN;

To generate the required RESET signal:

RESET: process

begin

Wait for 40ns;

RESET <='1';

Wait for 2ns;

RESET <='0';

end process RESET

b).

begin

if ( O /= "011" ) then report "ERROR";

end

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Figure 3(a) shows the waveforms to be generated using a VHDL test bench to simul

Figure 3-1 10 20 30 40 Quantity/Time 13. Which of the following is true regardin

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Figure 3(a) shows the waveforms to be generated using a VHDL test bench to simul

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