- A CMOS clocked SR flip-flop uses a technology with unCox = 100 uA/V^2, upCox =

Question

- A CMOS clocked SR flip-flop uses a technology with unCox = 100 uA/V^2, upCox = 25 uA/V^2, VDD = 2.5V, Vtn = -Vtp = 0.5V and the total capacitance at the output nodes equals 15fF. The inverter threshold voltage VM = 2.5V. The latch NMOS transistors Q1 and Q3 have (W/L)n = 1 um/0.5 um and the PMOS transistors Q2 and Q4 have (W/L)p = 2 um/0.5 um. 1. sketch the circuit showing SET, RESET, clock input and Q and Q' outputs. 2. propose for your design values of W/L of the SET and clock NMOS transistors and determine the associated SET time. Be aware that SET time will depend on your design and hence the optimum design is better rewarded.

Explanation / Answer

The problem can be solved by using a 4 phase clock. The idea is to sample the previous stage only after its evaluation is complete. In phase 1, node P is pre-charged. In phase 2, P as well as the output are pre- charged. In phase 3, The gate evaluates. In phases 4 and 1, the output is isolated from the driver and remains valid. This is called a type 3 gate. It evaluates in phase 3 and is valid in phases 4 and 1. Similarly, we can have type 4, type 1 and type 2 gates. A type 3 gate can drive a type 4 or a type 1 gate. Similarly, type Type 1 Type 2 Type 4 Type 3 Drive Sequences Figure 3.14: CMOS 4 phase dynamic logic drive constraints 4 will drive types 1 and 2; type 1 will drive types 2 and 3; and type 2 will drive 32 types 3 and 4. We can use a 2 phase clock if we stick to type 1 and type 3 gates (or type 2 and type 4 gates) as these can drive each other. 3.4.3 Domino Logic P A B C Ck

Related Questions

Navigate

• Browse (All)
• Browse #
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.