Describe any problems you had with using Quartus II and/or the eSOC III board. Q

Question

Describe any problems you had with using Quartus II and/or the eSOC III board.

Questions:

Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design?

In the compilation process, what is the difference between an error and a warning?

Use the zoom tool to measure the propagation delays, tPHL and tPLH, for the FPGA implementing the Design Project (the times between an input change of state and the subsequent output change of state in response). The zoom tool is used by expanding the time scale, right clicking on one signal, and selecting Insert Time Bar.

      tPHL =

      tPLH =

What is JTAG and why is it used? Be sure to cite your sources.

Explanation / Answer

I faced issue regarding comparing the theoretical floating point performance
of Field programmable gate arrays (FPGA) to micro processors.

1)Using the results of the compilation for the Design Project, what percent of the FPGA is used to implement the design?

Answer: To do this we implemented a single stream double square function
using c/c++ sysnthesis tool. this tool implements design using 2 percent of predicted
theoretical performance.

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2) warning : this is showing hint messages..minor mistakes so this doesnt make sense
for execution of program.
Error: there may be syntax erros..so so program don't execute.
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3) more accurately by enlarging the displayed simulation waveforms by
using the Zoom Tool. Left-click on the display to enlarge it and right-click to reduce it

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4)JOINT TEST ACTION TEST GROUP
JTAG tool is technolog where it is used for processor debug and emulation.
And also for programmiing FPGA's. Mainly it is used for boundary scan test.

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