The page table in Fig shows the mapping between 64-KB virtual address space and

Question

The page table in Fig shows the mapping between 64-KB virtual address space and 32-KB physical address space (the page size is 4 KB). Answer the following questions. Suppose, during the execution of a process, the MMU performs the following virtual address to physical address translations :

0011010001000001->000010001000001

0000010001000000->010010001000000

1011010001000011->111010001000011

0011010001001100->000010001001100

How many different entries (elements) of the page table are accessed by the MMU to produce the above translations? Which entries (elements) of the page table are they and what page frame numbers do these elements contain?

Outgoing physical address (24580) 15 000 14 000 0 13 000 0 12 000 0 10 000 0 9 101 1 8000 0 7 000 0 6000 0 5 011 1 4 100 1 3 000 1 2 110 1 1001 1 0 010 1 12-bit offset copied directly from inpuft to output Page table 110 Present/ absent bit Virtual page = 2 is used as an index into the page table Incoming virtual address (8196)

Explanation / Answer

The virtual page number is used as an index into the page table to find the entry for that virtual page. From the page table entry, the page frame number (it any) is found. The page frame number is attached to the high-order end of the offset, replacing the virtual page number, to form a physical address that can be sent to the memory.The purpose of the page table is to map virtual pages onto page frames. Mathematically speaking, the page table is a function, with the virtual page number as argument and the physical frame number as result. Using the result of this function, the virtual page field in a virtual address can be replaced by a page frame field, thus forming a physical memory address.

Despite this simple description, two major issues must be faced:

1.      The page table can be extremely large.

2.      The mapping must be fast.

The first point follows from the fact that modern computers use virtual addresses of at least 32 bits. With, say, a 4-KB page size, a 32-bit address space has 1 million pages, and a 64-bit address space has more than you want to contemplate. With 1 million pages in the virtual address space, the page table must have 1 million entries. And remember that each process needs its own page table (because it has its own virtual address space).

The second point is a consequence of the fact that the virtual-to-physical mapping must be done on every memory reference. A typical instruction has an instruction word, and often a memory operand as well. Consequently, it is necessary to make 1, 2, or sometimes more page table references per instruction, If an instruction takes, say, 4 nsec, the page table lookup must be done in under 1 nsec to avoid becoming a major bottleneck.

The need for large, fast page mapping is a significant constraint on the way computers are built. Although the problem is most serious with top-of-the-line machines, it is also an issue at the low end as well, where cost and the price/performance ratio are critical. In this section and the following ones, we will look at page table design in detail and show a number of hardware solutions that have been used in actual computers.

The simplest design (at least conceptually) is to have a single page table consisting of an array of fast hardware registers, with one entry for each virtual page, indexed by virtual page number, as shown in Fig. 4-11. When a process is started up, the operating system loads the registers with the process

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