Design a synchronous binary counter using three JK master-slave flipflops (havin

Question

Design a synchronous binary counter using three JK master-slave flipflops (having active high direct clear inputs) whose combinational circuit outputs (T1, T2, T3, and T4) produce a repeating sequence of four nonoverlapping clock pulses. (Hint: Use a modulo-8 binary counter each of whose outputs (T1, T2, T3, and T4) takes the value 1 for exactly one odd numbered state and takes the value 0 otherwise. Also note that the direct clear inputs on the flip-flops can be driven by a power-on reset circuit to clear al three flip-flops and initialize them to the zero state before starting the repeating count sequence by driving their clock inputs with a synchronizing clock oscillator signal.)

Explanation / Answer

Some counters count upwards from zero. So they can be called as up counters. But the counters which can count in the downward direction i.e. from the maximum count to zero are called down counters.

The countdown sequence for a 3-bit asynchronous down counter is as follows:

Thus counting takes place as follows

QC QB QA = 111, 110, 101, 100, 011, 010, 001, 000.

From this sequence, it is evident that FF-A should toggle at every negative going clock edge but FF-B should change its state only at those instants when QA changes from LOW (0) to HIGH (1) and QC should change only when QB changes from LOW to HIGH.

Thus in a down counter, each FF except the first one (FF-A) should toggle when the output of its preceding flip-flop changes from LOW to HIGH. If all the FFs are negative edge triggered i.e. responding to the negative CLK edge, then we can place an inverter in front of every CLK input or we can drive the CLK input of next FF from the Q¯Q¯ output of the preceding FF and not from the T outputs   

Decimal Qc Qb Qa 7 1 1 16 6 1 1 0 5 1 0 1 4 1 0 0 3 0 1 1 2 0 1 0 1 0 0 1 0 0 0 0

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