Design a sequential circuit displaying a \"heart-beat pattern with VHDL Design t
ID: 2084621 • Letter: D
Question
Design a sequential circuit displaying a "heart-beat pattern with VHDL Design the circuits in Section 4. We want to create a "heartbeat" for the prototyping board. It repeats a simple pattern in the four-digit seven-segment display, as shown below. The rate of the heartbeat can be 5 Hz (i.e., with a period of 200 ms), or 10 Hz (i.e., with a period of 100 ms), selectable by an external switch. Note that since there are four patterns in each heartbeat cycle, the period spent on each pattern is 50 ms and 25 ms, respectively. The circuit has the following inputs: clk: 50 MHz clock signal fast: select the faster 10-Hz rate when it is asserted. middotThe output of the stopwatch is four seven-segment LED displays The design must be synchronous: i.e., all FFs are driven by the same clock signal. Derive the conceptual diagram for the VHDL code (with registers, adders, muxes, etc).Explanation / Answer
VHDL code :
===============================
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity Heart is
Port ( clk : in STD_LOGIC;
fast : in STD_LOGIC;
reset : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (2 downto 0));
end Heart;
architecture Behavioral of Heart is
type state is (s1, s2, s3, s4);
signal CState : state;
signal temp: std_logic_vector (2 downto 0);
signal counter: std_logic_vector (23 downto 0);
signal clk2: std_logic;
begin
process(clk)
begin
if(reset='1')then
clk2<='0';
counter <= "000000000000000000000000";
elsif(rising_edge(clk))then
counter <= std_logic_vector (unsigned(counter)+ 1);
if(counter = "100110001001011010000000")then
counter <= "000000000000000000000000";
if(clk2='1')then
clk2<= '0';
else
clk2<= '1';
end if;
end if;
end if;
end process;
process(clk2)
begin
if(reset='1')then
temp <= "001";
Cstate <= s1;
elsif(rising_edge(clk2))then
case CState is
when s1 =>
temp <= "010";
Cstate <= s2;
when s2 =>
temp <= "100";
Cstate <= s3;
when s3 =>
temp <= "010";
Cstate <= s4;
when s4=>
temp <= "001";
Cstate <= s1;
end case;
end if;
end process;
led <=temp;
end Behavioral;
==================================
TESTBENCH:
================================
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY heatbeats IS
END heatbeats;
ARCHITECTURE behavior OF heatbeats IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Heart
PORT(
clk : IN std_logic;
fast : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal fast : std_logic := '0';
signal reset : std_logic := '1';
--Outputs
signal led : std_logic_vector(2 downto 0);
-- Clock period definitions
constant clk_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Heart PORT MAP (
clk => clk,
fast => fast,
reset => reset,
led => led
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 10 ns;
wait for clk_period*10;
reset <= '0';
-- insert stimulus here
wait;
end process;
END;
===========================
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