i know some of the currect answers a- Linearly c- After whats the other and why

Question

i know some of the currect answers

a- Linearly

c- After

whats the other and why

The 8086's 6-byte long prefetch queue was a structure that aided processor performance as long as the instruction execution sequence was implemented (with for-next loops/circularly/random ly/linearly/using many branches circle one). Externally, the 8086 had a __________________ address/data bus, which meant that the address signals and the data signals shared the same pins on the chip. This meant that the address had to be latched into external circuitry (before/alter circle one) the data was on the bus. To accomplish the latching, the 8086 (and 8088) had an additional pin, called ______________________ to allow the external circuitry to latch in the address. Upon reset, the CS register is loaded with _______ and the instruction pointer register is loaded with __________, for a real-mode physical address of ______________ hex.

Explanation / Answer

b. Multiplexd (because it carries both data and adddresss in multiplex mode)
d. ALE or Address Latch Enable (when 1, address data bus contains a memory or I/O address.)
e. FFFFh
f. 0000h
g. FFFF0h (because segmented address FFFFh:0000h, which maps to physical address FFFF0h)

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