A processor outputs the physical address BAAFBFF (in hex) with the following par

Question

A processor outputs the physical address BAAFBFF (in hex) with the following partitioning.

In answering the following questions, assume the memory space is Byte addressable and the parts (a - h) are not related to each other.

a. How many blocks does the main memory contain?

b. If Direct Mapped Cache is used, how many entries does the cache contain?

c. If Two-Way Set Associative Cache is used, how many entries does the cache contain?

d. If 4-Way Set Associative Cache is used, how many entries does the cache contain?

e. If 4-Way Set Associative Cache is used, what is the cache capacity?

f. If 4-way Set Associative is used, what is the number of segments in memory

g. If 4-way Set Associative is used, what is the cache address (entry) for the physical address generated? Show your answer in decimal.

h. Assume Fully Associative is used. Further assume that a program in execution can fit entirely into main memory. To ensure that a miss never occurs on a block once compulsory misses are satisfied, what should the minimum size of the cache be in bytes?

Explanation / Answer

Here processor generated a HexaDecimal address of length 7 characters.

Here Iam assuming that the main memory is capable to address all possible addresses with this address length(17). Means we can have atmost 16^7 addresses that each with 1 Byte data. our main memory has to be of size (16^7)*1Byte.

so,

Main Memory size = ((2^4)^7)*1Byte

                              = (2^28)*1Byte

                              = 256 MB

Here 7 bit address is divided into 3 fields for the purpose of some cache mapping. but

LSB 3 bits: to find word in a Block.

All other 4 MSB bits will represent total number of Blocks in MainMemory.

a) so, No. of Blocks in Main Memory = 16^4 = 65536 Blocks.

b) If Direct Mapped Cache is used there to split physical address, then

LSB 3 bits: to find word in a Block.

MSB 2 bits: for TAG field

Middle 2 bits: for finding Block.

so, No. of Blocks in such cache = 16^2 = 256 Cache Blocks.

c) If 2-way set associative is used, then

LSB 3 bits: to find word in a Block.

MSB 2 bits: for TAG field

Middle 2 bits: for finding Set in Cache.

so, No. of Sets in Cache = 16^2 = 256 Sets

Each Set contains 2 Blocks. Right?

so, No. of Blocks in such Cache = 256*2 = 512 Cache Blocks

d) If 4-way set associative cache is used, then

Each Set contains 4 Blocks. Right?

so, No. of Blocks in such Cache = 256*4 = 1024 Cache Blocks

e) If 4-way set associative cache is used, then Cache Capacity is

                         = 1024 Cache Blocks * 1 Cache Block Size

                         = 1024 * 1 Main Memory Block Size

                         = 1024 * 16^3 Bytes(Note: because LSB 3 bits are used to find a Word in Block)

                         = 2^22 Bytes = 4 MB (cache size excluding other bits like valid,tag info bits, etc...)

f) What is meant by Segment in memory? I don't understand.

g) cache size = 4 MB.

AF - Used to find Cache Set.

value of AF in decimal:

16*10 + 15 = 175 th Cache Set.

175*4 = 700   (Note: here 4 is No.of Blocks per Set)

We cannot say that this physical address is mapped to this particular cache address location. Because, this physical address can map to any 4 blocks of that set. Unless we know the tag field and if there any tag field match among those 4 blocks, we cannot say a particular cache location.

if we assume the first block's tag is matched with tag 'BA', then cache address in decimal:

(700*Block size) + decimal(BFF)

BFF in decimal:

256*11 + 16*15 + 15 = 3071 Word in 700th block.

Cache decimal address:

700*2^12 + 3071 = 700*4096 + 3071 = 2870271

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