It is an rchiticture class: Memory Hierarchy. The question is: Assuming the addr

Question

It is an rchiticture class: Memory Hierarchy.

The question is: Assuming the address is 32bits

a) What is the size of a process page table (in Bytes) for a 16KB page size?

b) The above page table is itself paged and the processor contains a TLB. Describe the translation process for the first instruction fetch in a program. Define any variables you may need.

c) Draw a complete block diagram for the memory hierarchy in this case, using a virtually-indexed, physically tagged L1 cache. Assume a fully associative TLB and the cache from Pr. 1a). Show the size of all fields (in bits).

Explanation / Answer

a) page table size= number of page entries in page table * page table entry size

since logical address and physical address is 32 bits the logical page table size is 2^32 bits

and since page size =16KB= 2^14 bits

= 2^32/2^14

= 2^(32-14) =2 ^18 bits page entries and if we consider additional bits to be around 4 bits

which is similar to 2MB

b)If there is a page table entry in TLB then CPU generates the physical address as soon as it looks up the first frame number which reduce the access time as it already in TLB unlike strainght forward approach which doubles the effect of access time.

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