We have to write and simulate a hex to seven segment display convert in VHDL. I
ID: 3804958 • Letter: W
Question
We have to write and simulate a hex to seven segment display convert in VHDL.
I got the code down, but I cant seem to get the test bench for the simulation to work.
This is not the test bench. But I need help writing the test bench code using a counter. Any help would be amazing.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity encoder is
Port (
x : in STD_LOGIC_VECTOR(3 downto 0);
a_to_g : out STD_LOGIC_VECTOR(6 downto 0)
);
end encoder;
architecture Behavioral of encoder is
begin
process(x)
begin
case x is
when "0000" => a_to_g <= "0000001";
when "0001" => a_to_g <= "1001111";
when "0010" => a_to_g <= "0010010";
when "0011" => a_to_g <= "0000110";
when "0100" => a_to_g <= "1001100";
when "0101" => a_to_g <= "0100100";
when "0110" => a_to_g <= "0100000";
when "0111" => a_to_g <= "0001101";
when "1000" => a_to_g <= "0000000";
when "1001" => a_to_g <= "0000100";
when "1010" => a_to_g <= "0001000";
when "1011" => a_to_g <= "1100000";
when "1100" => a_to_g <= "0110001";
when "1101" => a_to_g <= "1000010";
when "1110" => a_to_g <= "0110000";
when others => a_to_g <= "0111000";
end case;
end process;
end Behavioral;
Explanation / Answer
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY test_tb IS
END test_tb;
ARCHITECTURE behavior OF test_tb IS
signal clk : std_logic := '0';
signal bcd : std_logic_vector(3 downto 0) := (others => '0');
signal segment7 : std_logic_vector(6 downto 0);
constant clk_period : time := 1 ns;
BEGIN
uut: entity work.test PORT MAP (clk,bcd,segment7);
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
stim_proc: process
begin
for i in 0 to 9 loop
bcd <= conv_std_logic_vector(i,4);
wait for 2 ns;
end loop;
end process;
END;
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