10 In this exercise, we will look at the different ways capacity a ects overall
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Question
10 In this exercise, we will look at the different ways capacity a ects overall performance. In general, cache access time is proportional to capacity. Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2.
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KiB
8.0%
0.66 ns
P2
4 KiB
6.0%
0.90 ns
10.1 Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates?
10.2 What is the Average Memory Access Time for P1 and P2 (in cycles)?
10.3 Assuming a base CPI of 1.0 without any memory stalls,what is the total CPI for P1 and P2? Which processor is faster? (When we say a “base CPI of 1.0”, we mean that instructions complete in one cycle, unless either the instruction access or the data access causes a cache miss.)
For the next three problems, we will consider the addition of an L2 cache to P1 (to presumably make up for its limited L1 cache capacity). Use the L1 cache capacities and hit times from the previous table when solving these problems. The L2 miss rate indicated is its local miss rate.
L2 Size
L2 Miss Rate
L2 Hit Time
1 MiB
95%
5.62 ns
10.4 What is the AMAT for P1 with the addition of an L2 cache?Is the AMAT better or worse with the L2 cache?
10.5 Assuming a base CPI of 1.0 without any memory stalls, what is the total CPI for P1 with the addition of an L2 cache?
10.6 What would the L2 miss rate need to be in order for P1 with an L2 cache to be faster than P1 without an L2 cache?
10.7 What would the L2 miss rate need to be in order for P1 with an L2 cache to be faster than P2 without an L2 cache?
L1 Size
L1 Miss Rate
L1 Hit Time
P1
2 KiB
8.0%
0.66 ns
P2
4 KiB
6.0%
0.90 ns
Explanation / Answer
Per chegg policy, we can only provide the first four part of solution. Please request another quetion for rest :
10.1) P1 Cycle Time = 0.66 ns.
f 1 = 1/T = 1/(0.66 x 10-9 ) = 1.52 GHz
P2 Cycle Time = 0.90 ns.
f 2 = 1/T = 1/(0.90 x 10-9 ) = 1.11 GHz
10.2) AMAT = Hit Rate * Hit Time + Miss Rate x Miss Time
For P1: AMAT = 0.66 + (0.08)(70) = 6.26 ns
For P2: AMAT = 0.90 + (0.06)(70) = 5.10 ns
10.3) CPI = CPI + (Miss Rate) * (Memory Access Instruction) * (Miss Penalty)
For P1: CPI = 1 + (0.08)(1.36)(70/0.66) = 12.54 cycles/instruction
For P2: CPI = 1 + (0.06)(1.36)(70/0.90) = 7.34 cycles/instruction
10.4) Find AMAT for L2 cache: AMAT = Hit Time + (Miss Rate) x (Miss Latency)
AMAT = 5.62 + (0.95)(70) = 72.12 ns
Find AMAT for processor core: AMAT = Hit Time + (Miss Rate) x (Miss Latency)
AMAT = 0.66 + (0.08)(72.12) = 6.43 ns, worse than the AMAT for P1 found in part b .
10.5) CPI = CPI + (L1 Miss Rate) * (Memory Access Instruction) * (L1 Miss Penalty) + (L2 Miss Rate) * (Memory Access Instruction) * (L2 Miss Penalty)
CPI = 1 + (0.08)(1.36)(5.62/0.66) + (0.95*0.08)(1.36)(70/0.66) = 12.89 cycles/instruction
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