Procedure: Open a project, call it TOP. Open a new VHDL file then copy your adds

Question

Procedure:

Open a project, call it TOP.

Open a new VHDL file then copy your addsub code below:

Add plenty of comments to prove you know what the code is doing.

Save this file.

Do not compile yet!

Open a new VHDL file then complete the code below for the seven segment decoder.

Add plenty of comments to prove you know what the code is doing.

Open a new VHDL file then complete the code below for the TOP module that ties everything together as shown in figure 1.

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TOP is port

                                ( _____: ___________;

                              _____ : _____________________;

                           _____ : _____________________            );

end TOP;

architecture beh of TOP is

                signal rope1,rope2: std_logic_vector(3 downto 0); -- declare “ropes” that tie components

begin

                                A0: entity work.addsub(beh) port map

(1.__?__=>__?_, 2__?__=>__?__, 3__?__=>__?___,4__?___=>__?___,5__?__=>__?___);

                                A1: entity work.seven(beh) port map --this component is used twice

(1___?___=>___?___,2___?___=>___?___);

                           A2: entity work.seven(beh) port map

(1___?___=>___?___,2___?___=>___?___);

end beh;

Add plenty of comments to prove you know what the code is doing.

Save this file

Import pin assignments

Compile

Program then test your design

Figure 1: ADDERSUBTRACTOR. Procedure: 1. Open a project, call it TOP 2. open a new VHDL file then copy your addsub code below: LIBRARY ieee, use icee sad logic 1164 ALL: use ieee-std logic arith all use ieeeestd logic igned all ENTITY add sub IS in std logic vector(3 downto 0% in std logic vector(3 downto 0% in std logic. carry in: out std logic vector(3 downto o) out std logic carry out: END addsub ARCHITECTURE beh OF addsub IS signal result: std logic vector(4 downto 0) BEGIN PROCESS (carry in) BEGIN IF THEN

Explanation / Answer

% Logistics Map % Classic chaos example. Plots semi-stable values of % x(n+1) = r*x(n)*(1-x(n)) as r increases to 4. % % Michael Hanchak, Dayton OH, USA, 2011 clear scale = 10000; % determines the level of rounding maxpoints = 200; % determines maximum values to plot N = 3000; % number of "r" values to simulate a = 2.0; % starting value of "r" b = 4; % final value of "r"... anything higher diverges. rs = linspace(a,b,N); % vector of "r" values M = 500; % number of iterations of logistics equation % Loop through the "r" values for j = 1:length(rs) r=rs(j); % get current "r" x=zeros(M,1); % allocate memory x(1) = 0.5; % initial condition (can be anything from 0 to 1) for i = 2:M, % iterate x(i) = r*x(i-1)*(1-x(i-1)); end % only save those unique, semi-stable values out{j} = unique(round(scale*x(end-maxpoints:end))); end % Rearrange cell array into a large n-by-2 vector for plotting data = []; for k = 1:length(rs) n = length(out{k}); data = [data; rs(k)*ones(n,1),out{k}]; end % Plot the data figure(97);clf h=plot(data(:,1),data(:,2)/scale,'k.'); set(h,'markersize',1) axis tight set(gca,'units','normalized','position',[0 0 1 1]) set(gcf,'color','white') axis off

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