1. Consider a system with a byte-addressable virtual address space of 65536 byte
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Question
1. Consider a system with a byte-addressable virtual address space of 65536 bytes, and a physical address space of 64 32-bit words.
a. Assume that said system has an 8 entry cache with a block size of 8 bytes and an associativity of 1. Further assume that the cache is both virtually indexed and virtually tagged. If the cache entries are all initially invalid, what is the state of the cache (given as a table indicating the tuple for each cache set) after reads have been issued for word addresses 8, 6, 7, 5, 3, 0, 9?
b. What is the state of the cache if block size and capacity are held constant, but associativity increases to 2 with LRU replacement?
c. What is the state of the cache if block size and capacity are held constant, associativity increases to 2 with LRU replacement, and the cache is virtually indexed and physically tagged, assuming that there are 1KB pages and that the first 2 virtual pages (0 and 1) are mapped into the first two physical pages?
Explanation / Answer
Virtually all modern systems are byte-addressed, meaning that 32 bits can address about 4 gigabytes (if that much RAM is installed). Historically, there have been word-addressed schemes, with a "word" being bits, and likely some others, plus decimal machines which addressed a 4 or 6-bit unit. But also keep in mind that most modern systems employ virtual memory, meaning that the processor can address even more memory than what is installed.
entry cache with a block size of 8 bytes and an associativity of 1. Further assume that the cache is both virtually indexed and virtually tagged.
Virtually all modern systems are byte-addressed, meaning that 32 bits can address about 4 gigabytes (if that much RAM is installed). Historically, there have been word-addressed schemes, with a "word" being bits, and likely some others, plus decimal machines which addressed a 4 or 6-bit unit. But also keep in mind that most modern systems employ virtual memory, meaning that the processor can address even more memory than what is installed.
entry cache with a block size of 8 bytes and an associativity of 1. Further assume that the cache is both virtually indexed and virtually tagged.
- To access the first byte it has to skip 0 bytes, so first byte's address is 0.
- To access the second byte it has to skip 1 byte, so its address is 1.
- (and so forth...)
- To access the last byte, CPU skips 8, 6, 7, 5, 3, 0, 9bytes, so its address is 8, 6, 7, 5, 3, 0, 9
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