1A is done, need B,C,D Pipeline 1. Consider the processor with a five stage pipe
ID: 3779333 • Letter: 1
Question
1A is done, need B,C,D
Pipeline 1. Consider the processor with a five stage pipeline with delays listed in Table 1 IF MEM EX ID WB 300 ps 200 ps 250ps 350ps 150ps Table 1. Delay of each stage in the pipeline And assume that instructions percentage for each type is as follows LW ALU BEQ SW 45% 20% 20% 15% Table 2. Instructions' percentage a. What is the clock cycle for this processor with five stage pipeline? If use this stages in a non-pipeline design, what is the clock cycle?(ignore the delay of registers between different stages) b. Latency for an instruction is defined as the time that is needed for a single instruction to be executed. Calculate the latency for lw instruction in both pipeline and no-pipeline processor. Which one has a lower latency? c. Assume that you are allowed to split a stage into to equal stages. Which one do you prefer? Why? What is the new clock cycle for this design? d. If you run a program with 1000000 instructions, and we need to have 2 stall instructions after each BEQ instruction, and 5% of ALU instructions need a stall instruction, how much time is needed to finish this program using the pipeline processor with five stages ?(hint: calculate the CPI for each instruction type using the given information). If you run the same program with a non-pipeline processor, what is the execution time?Explanation / Answer
B)
Calculating latency for LW instruction:
Pipeline-Processor:
Latency = 5*350 =1750
Non-pipeline processor:
For non-pipeline processor the latency is the same as the cycle-time required to execute the instruction.
Latency = 1250
C)
Splitting the stages:
I split the ID stage into two stages because it is the longest-stage in the processor. By splitting the ID stage into, we can reduce the clock cycle-time.
The table below shows the cycle-time needed to execute each instruction type after ID stage is split into 2 stages.
Non-pipeline Processor
Instruction Type
IF
ID1
1D2
EX
MEM
WB
Total Time
ALU
250
175
175
150
200
950
BEQ
250
175
175
150
750
LW
250
175
175
150
300
200
1250
SW
250
175
175
150
300
1050
Pipeline Processor
Instruction Type
IF
ID1
1D2
EX
MEM
WB
Total Time
ALU
250
175
175
150
200
175
BEQ
250
175
175
150
175
LW
250
175
175
150
300
200
175
SW
250
175
175
150
300
175
Non-pipeline Processor
Instruction Type
IF
ID1
1D2
EX
MEM
WB
Total Time
ALU
250
175
175
150
200
950
BEQ
250
175
175
150
750
LW
250
175
175
150
300
200
1250
SW
250
175
175
150
300
1050
Pipeline Processor
Instruction Type
IF
ID1
1D2
EX
MEM
WB
Total Time
ALU
250
175
175
150
200
175
BEQ
250
175
175
150
175
LW
250
175
175
150
300
200
175
SW
250
175
175
150
300
175
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