(b) (10 points) Complete the VHDL architecture below for the unsigned 12-bit Add

Question

(b) (10 points) Complete the VHDL architecture below for the unsigned 12-bit Adder_Subtracter using behavioral style VHDL. The mode signal when 'o makes an adder, when 1 makes a subtracter The error signal is the Most Significant Bit (MSB) of the signal s tmp (indicates over/underflow)y library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all entity adder_subtracter is port (x, y: in unsigned(11 downto O); s: out unsigned(11 downto 0); mode : in std_logic; error: out std_logic ); end entity adder_ subtracter; architecture behavior of adder_subtracter is signal s tmp: unsigned(12 downto O); begin Concurrent equations end behavior;

Explanation / Answer

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity adder_subtractor is

port ( x, y : in unsigned (11 downto 0);

s : out unsigned (11 downto 0);

mode : in std_logic;

error : out std_logic );

end entity adder_subtractor;

architecture behavioral of adder_subtracter is

signal s_tmp : unsigned(12 downto 0);

begin -- concurrent equations

s_temp <= (x + y) when mode = '0' else (x - y);

s <= s_temp(11 downto 0);

error <= (s_tmp(12) and (not mode)) or ((not s_tmp(12) and mode);

end behavioral;

Condition for Overflow :

For Adder : If the Carry out is set to '1' while adding the two numbers then overflow = '1'

For Subtraction : If the Carry out is set to '0', while subtracting two numbers then underfow = '1'

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