2. Examine the difficulty of adding a proposed swap Rd, Rn instruction to the LE

Question

2. Examine the difficulty of adding a proposed swap Rd, Rn instruction to the LEGv8 instruction set, which works as follows: Reg[Rd] = Reg[Rn]; Reg[Rn] = Reg[Rd]; (20 pts)

a. Which new functional blocks (if any) do we need for this instruction? (4 pts)

b. Which existing functional blocks (if any) require modification? (4 pts)

c. What new datapaths do we need (if any) to support this instruction? (4 pts)

d. What new control unit signals (if any) do we need for this instruction? (4 pts)

e. Modify the complete control and datapath Figure to demonstrate the implementation of this new instruction.

Explanation / Answer

Please find my answer for 3 Quetions.

I have written the Instruction set for the repective Interpretation:-

a) Let me explain you the process of load with increment which can be done in two ways:-

i) Firstly read port in Registers basically to define read Rn and next by choosing a alternative ALU to add Rn to Rp +
Rq or Finally a third input to the actual ALU,
ii) Last step is to extend the actual ALU to perform the shifts and simultaneously adding the SLL ALU operations.

b)

i)First of all, The instruction adopts the instruction memory, both actual read ports like ALU, Registers and
the write port.
ii). After that, Make sure one of the actual register read ports have the lane
that reached immediate to the ALU, and the register write port.

d)
i)In this step, we need to focus more on a controlling of a signal which tells the Arithmetic logic unit to perform the specific task.
ii) Next, This time we need to differenciate the ALU Operations to control signals which adds the SLL modiifcation to it.

Interprepation Set:

ADDI Rs,Ra, Imm12: Reg[Rd] = Reg[Rn].
ADDS Rb, Ra, Rz: Reg[Ra] = Reg[Rs] + Reg[Rb].
B Imm26: PC = PC

B.LT Imm19: PC = PC.

BL Imm26: X30 = PC + 4 , PC = PC

BR Rd: PC = Reg[Rd].

CBZ Rt, Imm19: If (Reg[Rt] == 0) PC = PC

LDUR Rt, [Rn, #Imm9]: Reg[Rt] = Mem[Reg[Rn]

STUR Rt, [Rn, #Imm9]: Mem[Reg[Rn] +
SUBS Rd, Rn, Rm: Reg[Rd] = Reg[Rn] - Reg[Rm].

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