Department of Computer Science Morgan State University COSC 243 Computer Archite
ID: 3703740 • Letter: D
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Department of Computer Science Morgan State University COSC 243 Computer Architecture Spring 2018 Homework Assignment 5 (100 points) Due: April 13, 2018 by 11.59 pm Answer the following questions based on Chapter 4 of your text book. Type your answers/response for each in a report, and submit the report through Black Board. Possible score point for each exercise is also mentioned bellow. Show your work and cite accordingly if/where applicable Question 1. (5x3-15 points) Explain, in brief, the steps/actions in the datapath for the following a. R-type instruction b. Load/Store instruction c. Branch instruction Question 2. (15+15-30 points) Assume time for datapath stages are o 200 ps for register read or write o 300ps for other stages Compare pipelined datapath with single-cycle datapath in terms of time performance for a. Load instruction b. Branch instruction Question 3. (20+15-35 points) A program contains 10 instructions each going through 5 stages of MIPS pipeline. If the stages are assumed to be balanced (e.g. each stage takes similar time) a. Show the pipeline stages for the program b. Compare the speed-up using pipelining over single-cycle Question 4. (20 points) What is hazards in pipelining? Explain different types of pipeline hazards. Book: Computer Organization and Design: The Hardware/Software Interface, Patterson d Hennessy, Morgan Kaufmann, 5th Edition.Explanation / Answer
Answering 1 and 4 questions
1) a. R-Type Instruction
The R-format instructions They all read two registers, perform an ALU operation on the contents of the registers, and write the result to a register. We call these instructions either R-type instructions or arithmetic-logical instructions (since they perform arithmetic or logical operations). Th is instruction class includes add, sub, AND, OR, and slt.Th e processor’s 32 general-purpose registers are stored in a structure called a register file. R-format instructions have three register operands, so we will need to read two data words from the register fi le and write one data word into the register fi le for each instruction.
b) The load/store datapath uses instructions such as lw $t1, offset($t2), where offset denotes a memory address offset applied to the base address in register $t2. The lw instruction reads from memory and writes into register $t1. The sw instruction reads from register $t1 and writes into memory. In order to compute the memory address, the MIPS ISA specification says that we have to sign-extend the 16-bit offset to a 32-bit signed value.
The load/store datapath performs the following actions in the order given:
Register Access takes input from the register file, to implement the instruction, data, or address fetch step of the fetch-decode-execute cycle.
Memory Address Calculation decodes the base address and offset, combining them to produce the actual memory address. This step uses the sign extender and ALU.
Read/Write from Memory takes data or instructions from the data memory, and implements the first part of the execute step of the fetch/decode/execute cycle.
Write into Register File puts data or instructions into the data memory, implementing the second part of the execute step of the fetch/decode/execute cycle.
c) Branch Instruction : The branch datapath had two operations:
branch taken
A branch where the branch condition is satisfi ed and the program counter (PC) becomes the branch target. All unconditional jumps are taken branches.
branch not taken or (untaken branch)
A branch where the branch condition is false and the program counter (PC) becomes the address of the instruction that sequentially follows the branch.
4) There are situations, called hazards, that prevent the next instruction in the instruction stream from being executing during its designated clock cycle. Hazards reduce the performance from the ideal speedup gained by pipelining.
There are three classes of hazards:
Structural Hazards. They arise from resource conflicts when the hardware cannot support all possible combinations of instructions in simultaneous overlapped execution.
Data Hazards. They arise when an instruction depends on the result of a previous instruction in a way that is exposed by the overlapping of instructions in the pipeline.
Control Hazards.They arise from the pipelining of branches and other instructions that change the PC.
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