I have asked this question several times but keep getting the obvious response i

Question

I have asked this question several times but keep getting the obvious response i can lookup myself online. Trying to look for other ideas to reduce the number of wires from floppy to FPGA from 3 to 1 wire.

working on a floppy music design project, and we intend to use 32 floppies for the design.To control a floppy drive, we need three signals to feed into the floppy drive. The first signal, /STEP, will be a square wave at a certain frequency to play that note. The second signal, /DIR, controls the direction the head moves.The third signal, /EN, turns the floppy drive and it’s LED.

I'm looking for ways to reduce the number of wires required to control the floppies through logical or analog circuitry. will love to reduce the number of wires on each floppy from 3 wires to possibly 2 or 1. This reduction will increase the number of floppies on a microcontroller, thereby minimizing cost of production. I'm looking into the possibilities of using a 555 timer IC or a frequency divider. Any ideas ideas with circuitry will be greatly appreciated.

Basically the FPGA/microcontroller will control which floppy drive will play what note. The reduced wire protocol is an attempt to reduce the number of wires required to control the floppy drive by manipulating the square wave (or possibly other wave) fed to the floppy drive.

can u please draw a better schematic with details on the pin number allocations from the FPGA to the 555 timer, and from the 555 timer to the floppy. other ideas in mind are welcomed

Thanks very much!

You didn't specify what info u need. please tell me what info u need, and give me the opportuninty to update the question again. thanks

Computer communicates with the FPGA via serial communication. Inside the serial commands is an ID tag. This ID tag tells the FPGA which pin it should pulse. That pin is connected to one floppy drive. Using the RWP(reduced wire protocol) the floppy will then come to life and play the frequency that the FPGA is feeding it. The computer will read the MIDI file which, yes, will tell which floppy to play and at which frequency, but only in software. We have to convert that software into hardware.

Explanation / Answer

The monostable mode is also called “one-shot” pulse generator. The sequence of events starts when a negative going trigger pulse is applied to the trigger comparator. When this trigger comparator senses the short negative going trigger pulse to be just below the reference voltage (1/3 VCC), the device triggers and the output goes HIGH.

The discharge transistor is turned OFF and the capacitor C that is externally connected to its collector will start charging to the max value through the resistor R. The HIGH output pulse ends when the charge on the capacitor reaches 2/3 VCC. The internal connection of the IC 555 in monostable mode along with the RC timing circuit

The detailed operation can be explained as follows. Initially, the flip-flop is RESET. This will allow the discharge transistor to go to saturation. The capacitor C, which is connected to the open collector (drain in case of CMOS) of the transistor, is provided with a discharge path. Hence the capacitor discharges completely and the voltage across it is 0. The output at pin 3 is low (0).

When a negative going trigger pulse input is applied to the trigger comparator (comparator 2), it is compared with a reference voltage of 1/3 VCC. The output remains low until the trigger input is greater than the reference voltage. The moment trigger voltage goes below 1/3 VCC, the output of comparator goes high and this will SET the flip-flop. Hence the output at pin 3 will become high.

At the same time, the discharge transistor is turned OFF and the capacitor C will begin to charge and the voltage across it rises exponentially. This is nothing but the threshold voltage at pin 6. This is given to the comparator 1 along with a reference voltage of 2/3 VCC. The output at pin 3 will remain HIGH until the voltage across the capacitor reaches 2/3 VCC.

The instance at which the threshold voltage (which is nothing but the voltage across the capacitor) becomes more than the reference voltage, the output of the comparator 1 goes high. This will RESET the flip-flop and hence the output at pin 3 will fall to low (logic 0) i.e. the output returns to its stable state. As the output is low, the discharge transistor is driven to saturation and the capacitor will completely discharge.

Hence it can be noted that the output at pin 3 is low at start, when the trigger becomes less than 1/3 VCC the output at pin 3 goes high and when the threshold voltage is greater than 2/3 VCC the output becomes low until the occurrence of next trigger pulse. A rectangular pulse is produced at the output. The time for which the output stays high or the width of the rectangular pulse is controlled by the timing circuit i.e. the charging time of the capacitor which depends on the time constant RC.

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