PLEASE READ FULLY Answer parts A and C using VHDL. Implement this problem using
ID: 3600477 • Letter: P
Question
PLEASE READ FULLY
Answer parts A and C using VHDL. Implement this problem using a ONE-HOT finite state machine rather than a PLA. I understand their is already an answer posted using VERILOG...I DO NOT WANT THAT ANSWER PLEASE IT HAS TO BE IN VHDL CODE. Thanks
5.15 (a) Write VHDL code that describes the following SM chart. Assume that state changes occur on the falling edge of the clock. Use two processes. S2/0 SI/ZI zl 23 XI X3 (b) The SM chart is to be implemented using a PLA and two flip-flops (A and B). Complete the state transition table (PLA table) by tracing link paths. Find the equation for A by inspection of the PLA table (c) Complete the following timing diagram XI X2 ZlExplanation / Answer
-- Architecture definition for the SimpleFSM entity
Architecture RTL of SimpleFSM is
TYPE State_type IS (A, B, C, D); -- Define the states
SIGNAL State : State_Type; -- Create a signal that uses
-- the different states
BEGIN
PROCESS (clock, reset)
BEGIN
If (reset = ‘1’) THEN -- Upon reset, set the state to A
State <= A;
ELSIF rising_edge(clock) THEN -- if there is a rising edge of the
-- clock, then do the stuff below
-- The CASE statement checks the value of the State variable,
-- and based on the value and any other control signals, changes
-- to a new state.
CASE State IS
-- If the current state is A and P is set to 1, then the
-- next state is B
WHEN A =>
IF P='1' THEN
State <= B;
END IF;
-- If the current state is B and P is set to 1, then the
-- next state is C
WHEN B =>
IF P='1' THEN
State <= C;
END IF;
-- If the current state is C and P is set to 1, then the
-- next state is D
WHEN C =>
IF P='1' THEN
State <= D;
END IF;
-- If the current state is D and P is set to 1, then the
-- next state is B.
-- If the current state is D and P is set to 0, then the
-- next state is A.
WHEN D=>
IF P='1' THEN
State <= B;
ELSE
State <= A;
END IF;
WHEN others =>
State <= A;
END CASE;
END IF;
END PROCESS;
-- Decode the current state to create the output
-- if the current state is D, R is 1 otherwise R is 0
R <= ‘1’ WHEN State=D ELSE ‘0’;
END rtl;
library IEEE;
use IEEE.std_logic_1164.all;
-- this is the entity
entity ANDGATE is
port (
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end entity ANDGATE;
-- this is the architecture
architecture RTL of ANDGATE is
begin
O <= I1 and I2;
end architecture RTL;
DFF : Q <= '0' when RST = '1' else D when rising_edge(clk);
DFF : process(RST, CLK) is
begin
if rising_edge(CLK) then
Q <= D;
Q2 <= Q1;
end if;
if RST = '1' then
Q <= '0';
end if;
end process DFF;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; -- for the unsigned type
entity COUNTER is
generic (
WIDTH : in natural := 32);
port (
RST : in std_logic;
CLK : in std_logic;
LOAD : in std_logic;
DATA : in std_logic_vector(WIDTH-1 downto 0);
Q : out std_logic_vector(WIDTH-1 downto 0));
end entity COUNTER;
architecture RTL of COUNTER is
signal CNT : unsigned(WIDTH-1 downto 0);
begin
process(RST, CLK) is
begin
if RST = '1' then
CNT <= (others => '0');
elsif rising_edge(CLK) then
if LOAD = '1' then
CNT <= unsigned(DATA); -- type is converted to unsigned
else
CNT <= CNT + 1;
end if;
end if;
end process;
Q <= std_logic_vector(CNT); -- type is converted back to std_logic_vector
end architecture RTL;
process
begin
CLK <= '1'; wait for 10 NS;
CLK <= '0'; wait for 10 NS;
end process;
process
begin
wait until START = '1'; -- wait until START is high
for i in 1 to 10 loop -- then wait for a few clock periods...
wait until rising_edge(CLK);
end loop;
for i in 1 to 10 loop -- write numbers 1 to 10 to DATA, 1 every cycle
DATA <= to_unsigned(i, 8);
wait until rising_edge(CLK);
end loop;
-- wait until the output changes
wait on RESULT;
-- now raise ACK for clock period
ACK <= '1';
process (CLOCK)
begin
if CLOCK'event and CLOCK = '1' then
if DIRECTION = '1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
wait until rising_edge(CLK);
ACK <= '0';
-- and so on...
end process;
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