Update: Both screenshots are apart of the same problem so the full instructions

ID: 3349615 • Letter: U

Question

Update: Both screenshots are apart of the same problem so the full instructions are shown.

Update 2: Nothing other than what was shown was given for the problem

For this question, assume the inital state of an LC-3 processor as shown below. The PC is set to x3D00. Perform the fetch-decode-execute cycle as the LC-3 would, up to (but not includingl the HALT trep. ncther words, stop executing when the progran reaches the HALT. Do not fetch or execute that instruction. Initial Register Values Register Value 116-bit hex) RO R1 x0001 xFFFF XABCO x3000 xF025 x0000 x7FFF x0040 F4 R5 R6 R7 Memory Contents Address Contents (binary) x3000 00100000000001 10 x3001 00001000000D0001 x3002 1001000000111111 x3003 1001000000111111 x3005 1001000000111111 x3006 1111000000100101 excluding HALT), indicate he final values or the general purpose re isters and or the condition code bits. The e ister values must be entered in 16-bit hexadecimal, such as x000C instead of XC or #10 Once you have executed the instructions etc.) code bits are just one bit (0 or 1) Final State, after Execution Condition Code BitValue

Explanation / Answer

0010 is code for load

Next 3bits desti. Reg (r0)

9 bit offset(000000110)

R0<-PC+000000110

0000 is for branch

Next 3bits(100) indicates n z p

Remaining 9 bits pc offset

If n=1,z&p=0 then PC<-PC+offset

1001 means not

Next 6bits source and destination reg (R0&R0)

Remaining 7bits are 1's

0000 is indicate branch instruction

010 is nzp values

111111110 is pc offset

If z=1&n,p=0 then

Pc=pc+offset

Pc=3202

1001 is for not

Next 6bits source and destination

Remaining all 1's

0000 means branch instruction

If nzp=0

Address code comments updated register values 0x3000 0010 0000 0000 0110