Lab #8-3-bit Adder with BCD/Seven Segment Display Decoder Introduction Addition

Question

Lab #8-3-bit Adder with BCD/Seven Segment Display Decoder Introduction Addition of n-bit binary numbers requires the use of a full adder, and the process of addition proceeds on a bit- by-bit basis, right to left, beginning with the least significant bit. After the least significant bit, addition at each position adds not only the respective bits of the words, but must also consider a possible carry-in bit from addi- tion at the previous position. Adders. A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. Addition of n-bit numbers requires a chain of n full adders where the input carry to the least significant position is fixed at 0 a3 b3 a2 b2 al bl a b cin 1+0 0-01 a b+cin b cin +0+1:01 a b cin 11+0 10 a+ b cin +0-10 a+ b+cin a+b+cin cout cout s2 s1 s0 An -bit adder can be easily implemented in Verilog HDL using Dataflow or Behavioral Modeling through Arithmetic Operators. The developer must define the input and sum register sizes appropriately. For example, the line reg [4:0] R defines a 5-bit register named R. This register can also be assigned as an input or output. BCD. Codes and Number Systems are both represented by a series of binary digits, but are very different when interpreted. Number Systems have place value based on the Radix (or base), and have specific rules for arithme tic operations. Hexadecimal (base-16) is special because it is both a code and a number system. The binary number system (base-2) is the most natural system for a computer because it is readily represented in today's

Explanation / Answer

module fulladder ( // Single bit Adder
  input A,
  input B,
  input Cin,
  output Sum,
  output Cout
);

assign Sum = A ^ B ^ Cin;
assign Cout = (A & B) | (A & Cin) | (B & Cin);

endmodule

module fulladder_Nbit #( // N bit full adder
   parameter WIDTH = 4
) (
  input [WIDTH-1:0] A,
  input [WIDTH-1:0] B,
  input Cin,
  output [WIDTH-1:0] Sum,
  output Cout
);

wire [WIDTH:0] w;

assign w[0] = Cin;
assign Cout = w[WIDTH];

genvar i;
  generate
   for(i = 0; i < WIDTH; i = i + 1)
   begin : FULL_ADDER
   fulladder U (.A(A[i]), .B(B[i]), .Cin(w[i]), .Sum(Sum[i]), .Cout(w[i+1]));
   end
  endgenerate

endmodule

module sevensegment(
  input [3:0] in1,
  output reg [6:0] out1
);

always @(in1)
  begin
   case(in1)
   4'd0 : out1 = 7'b111_1110;
// represents 0 in SSD
   4'd1 : out1 = 7'b011_0000;
// represents 1 in SSD
   4'd2 : out1 = 7'b110_1101;
// represents 2 in SSD
   4'd3 : out1 = 7'b111_1001;
// represents 3 in SSD
   4'd4 : out1 = 7'b011_0011;
// represents 4 in SSD
   4'd5 : out1 = 7'b101_1011;
// represents 5 in SSD
   4'd6 : out1 = 7'b101_1111;
// represents 6 in SSD
   4'd7 : out1 = 7'b111_0000;
// represents 7 in SSD
   4'd8 : out1 = 7'b111_1111;
// represents 8 in SSD
   4'd9 : out1 = 7'b111_1011;
// represents 9 in SSD
   default : out1 = 7'b111_1110;
// represents 0 in SSD
   endcase
  end

/*/////// TRUTH TABLE FOR SEVEN SEGMENT DISPLAY ////////////
=======================================================
|| Decimal || a | b | c | d | e | f | g |
=======================================================
|| 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 |
|| 1 || 0 | 1 | 1 | 0 | 0 | 0 | 0 |
|| 2 || 1 | 1 | 0 | 1 | 1 | 0 | 1 |
|| 3 || 1 | 1 | 1 | 1 | 0 | 0 | 1 |
|| 4 || 0 | 1 | 1 | 0 | 0 | 1 | 1 |
|| 5 || 1 | 0 | 1 | 1 | 0 | 1 | 1 |
|| 6 || 1 | 0 | 1 | 1 | 1 | 1 | 1 |
|| 7 || 1 | 1 | 1 | 0 | 0 | 0 | 0 |
|| 8 || 1 | 1 | 1 | 1 | 1 | 1 | 1 |
|| 9 || 1 | 1 | 1 | 1 | 0 | 1 | 1 |
=======================================================
*/

endmodule


module bcd_adder_3bit ( // Top module for BCD addition
  input [2:0] A,
  input [2:0] B,
  input Cin,
  output [6:0] sevenout1
);

wire [2:0] Sum;
wire Cout;
wire [3:0] wire1;

assign wire1 = {Cout, Sum};

// Adder instantiation for 3 bit so overriding the WIDTH to 3bit
fulladder_Nbit #(.WIDTH (3)) m1 (.A(A), .B(B), .Cin(Cin), .Sum(Sum), .Cout(Cout));

// Seven Segment instantiation
sevensegment m2 (.in1(wire1), .out1(sevenout1));

endmodule

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