1.) Given the following Core Clock Frequency and register settings for the 9S12,

Question

1.) Given the following Core Clock Frequency and register settings for the 9S12, supply the parameters for the PWM waveform produced on Channel 5.

fCore = 21.4 MHz

PWMPRCLK=0x73

PWMSCLA=0xE6

PWMSCLB=0x05

PWMCLK=0xB4

PWMPOL=0xF5

PWMCAE=0xFE

PWMCTL=0x40

PWMPER0=0xA8 PWMDTY0=0x8B

PWMPER1=0x9E PWMDTY1=0x79

PWMPER2=0x98 PWMDTY2=0x88

PWMPER3=0x8A PWMDTY3=0x6E

PWMPER4=0xCA PWMDTY4=0xAD

PWMPER5=0xB7 PWMDTY5=0x96

PWMPER6=0x97 PWMDTY6=0x83

PWMPER7=0x6F PWMDTY7=0x63

For Channel 5:

PWMPeriod = ?? ms

PWM Time High = ?? ms

PWM Duty = ?? %

Explanation / Answer

We are interested in the channel 5 behaviour
fCore = 21.4 MHz
PWMPRCLK=0x73 -> PCKA = 3 -> Clock A = Fbus/8
PWMSCLA=0xE6 -> 230 -> Clock SA = Clock A / 230
PWMSCLB=0x05 -> not an issue we need only clock SA
PWMCLK=0xB4 -> PCLK5 = 1 -> Clock SA is the clock source for PWM channel 5.
PWMPOL=0xF5 -> PPOL5 = 1 -> PWMchannel 5 output is high at the beginning of the period, then goes low when the duty count is reached.
PWMCAE=0xFE -> CAE5 = 1 -> Channel 5 operates in Center Aligned Output Mode
PWMCTL=0x40 -> CON45 = 1 -> channel 4 and 5 are concatenated and the clock selection is depended on channel 5

PWMPER4=0xCA PWMDTY4=0xAD
PWMPER5=0xB7 PWMDTY5=0x96

channel 4 is the high byte and channel 5 is low byte

so total period register would be 16 bits, right 8 bits are of PWMPER5 and left 8 bits are PWMPER4
so PER = 0xCAB7 = 51895
and DTY = 0xAD96 = 44438
clock used is clock SA = clock A / 230 = fBus/(8*230)
period of clock SA = ((8*230)/21.4) micro s = 85.98
SO period = 51895 * 2 * 85.98 = 8924000 micro s = 8.924 s ( a factor of 2 is added as it is center aligned)
and duty = 44438/51895 = 85.6%
and high time is period * duty = 7.64 s

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