QUESTION 1 How many possible states can be represented by a 5-bit state register
ID: 2291345 • Letter: Q
Question
QUESTION 1
How many possible states can be represented by a 5-bit state register?
QUESTION 2
When a clock signal changes from 1 to 0, this is referred to as the...
Period
Falling edge
Rising edge
Frequency
QUESTION 3
What is the minimum number of bits required in order for a state register to represent an FSM with 24 states?
0.5 points
QUESTION 4
What is the clock period for a clock with a frequency of 16 MHz?
Note: This answer will be autograded. Please include units with a single space between the number and the units.
QUESTION 5
What is the frequency of a clock with a period of 50 ms?
Note: This answer will be autograded. Please include units with a single space between the number and the units.
QUESTION 6
How many possible states can be represented by a 10-bit state register?
QUESTION 7
What is the clock period for a clock with a frequency of 3.2 GHz?
Note: This answer will be autograded. Please include units with a single space between the number and the units.
QUESTION 8
When a clock signal changes from 0 to 1, this is referred to as the...
Period
Falling edge
Rising edge
Frequency
QUESTION 9
What is the frequency of a clock with a period of 500 ns?
Note: This answer will be autograded. Please include units with a single space between the number and the units.
QUESTION 10
What is the minimum number of bits required in order for a state register to represent an FSM with 6 states?
Period
Falling edge
Rising edge
Frequency
Explanation / Answer
1. number of possible states = 25 =32
2. Falling edge when clock changes from 1 to 0
4. clock period = 1/(16x106) = 62.5x10-9 s =62.5 ns
5. frequency of a clock with a period of 50 ms = 1/(50x10-3) = 20 Hertz
6. number of possible states = 210= 1024 states
7. clock period for a clock with a frequency of 3.2 GHz = 1/(3.3x109) = 312.5x10-12 = 312.5 picoseconds
8. When a clock signal changes from 0 to 1, this is referred to as the Rising Edge
9. frequency of a clock with a period of 500 ns = 1/(500x10-9) = 2 MHz
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7.
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