Practice with VHDL PROCESS Statement for Shift Registers and Counters R13:01 4 S
ID: 2290855 • Letter: P
Question
Practice with VHDL PROCESS Statement for Shift Registers and Counters R13:01 4 SRAP SR4 InBit InBit Clock Clock (b) Like Fig. 7.19 in text: 4-bit Shift Register with capabil for parallel loading ("Paralkel-access" (a) Like Fig. 7.18 in text: 4-bit Shift Register Figure 1: Two 4-bit Shift Registers 1. Complete this VHDL to implement fig. 1(a): -entity SR4 library ieee. use ieee.std_logic_1164.a11; entity SR4 is port( InBit,Clock: in std.logic end SR4; architecture behavorial of SR4 is OutBit: out std_logic); signal Q: std.logic.vector(1 to 4)0oo" --ignal Q is the 4-bit regiater begin PROCESS (Clock) begin if rising.edge(Clock) then Q(2) Q(3) Q(4)Explanation / Answer
1.
-- entity SR4
library ieee
use ieee.std_logic_1164.all;
entity SRP4 is
port(InBit,Clock:in std_logic;
OutBit:out std_logic);
end SRY;
architechural behavioral of SR4 is
signal Q:std_logic_vector(1 to 4):="0000";
begin
PROCESS (clock)
begin
if rising-edge(clock) then
Q(1) <= InBit;
Q(2) <= Q(1);
Q(3)<= Q(2);
Q(4)<= Q(3);
end if;
end PROCESS;
OutBit <=Q(4);
end behavioral;
2. ans->
-- entity SR4P
library ieee
use ieee.std_logic_1164.all;
entity SR4P is
port(InBit,Clock,L:in std_logic;
R:in std_logic_vector(3 downto 0);
OutVec:out std_logic_vector(3 downto 0));
end SR4P;
architechural behavioral of SR4P is
signal Q:std_logic_vector(3 downto 0):="0000";
begin
PROCESS (clock)
begin
if rising-edge(clock) then
if L='1' then
Q[3:0]<= {R[3:0]};
else
Q(1) <= Q(2) ;
Q(2) <= Q(1);
Q(3)<= Q(0);
Q(4)<= InBit;
end if;
end if;
end PROCESS;
OutVec <=Q;
end behavioral;
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