5) Complete the hierarchical VHDL code below to implement the AOl circuit. The d

Question

5) Complete the hierarchical VHDL code below to implement the AOl circuit. The design consists of four design files. There is an AND design, INV design and OR design. Each design is implemented using a CASE statement to show various CASE configuration. int I AND GATE: hw11 p5_ and. vhd library IEEE; use IEEE STD LOGIC 1164 ALL: entity hw11 p5_and is Port (signal in1, in2: in STD LOGIC; signal out STD LOGIC); end hw11 p5 and; architecture behavioral of hw11 p5 and is begin process (in1, ) is begin case std logic vector(in1, in2) is when "11and out1 when others => and-out : end case end process; end behavioral OR GATE: hw11 p5 or shad library EEE; use IEEE STD LOGIC 1164 ALL entity hw11 p5_or is Port (signal in STD LOGIC; signal or out:out STD LOGIC) end hw11_p5 or architecture behavioral of hw11_pS_or is begin process (in1, in2) is begin case std logic_vector (in1, in2) is a list of cases to check separated by I when "01-1-10-1 when others orout => or out

Explanation / Answer

AND GATE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hw11_p5_and is
port(signal in1,in2:in STD_LOGIC;
signal and_out :out STD_LOGIC);
end hw11_p5_and;
architecture behavioral of h1_p5_and is
begin
process(in1,in2) is begin
case std_logic_vector(in1,in2) is
when "11"=> and_out<='1';
when others=> and_out<='0';
end case;
end process;
end behavioral;

OR GATE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hw11_p5_or is
port(signal in1,in2 :in STD_LOGIC;
signal or_out :out STD_LOGIC);
end hw11_p5_or;
architecture behavioral of h1_p5_or is
begin
process(in1,in2) is begin
case std_logic_vector(in1,in2) is
--a list of cases to check seperated by |
when "01"|"10"|"11 " => or_out<='1';
when others=> or_out<='0';
end case;
end process;
end behavioral;

INVERTER:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity hw11_p5_inv is
port(signal inv_in:in STD_LOGIC;
signal inv__out :out STD_LOGIC);
end hw11_p5_inv;
architecture behavioral of hw1_p5_inv is
begin
process(inv_in) is begin
case inv_in is
--single bit,single quote
when '0'=> inv_out<='1';
when others=> inv_out<='0';
end case;
end process;
end behavioral;

WHOLE CIRCUIT:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity hw11_p5 is
port(signal A,B,C:in STD_LOGIC;
signal F :out STD_LOGIC);
end hw11_p5;
architecture behavioral of h1_p5 is
signal int1,int2:STD_LOGIC;
begin

and0:entity work.hw_p5_and
port map(in1=>B,in2=>C,and_out=>int1);

inv0:entity work.hw_p5_inv
port map(inv_in=>A,inv_out=>int2);

or0:entity work.hw_p5_or
port map(in1=>int1,in2=>int2,or_out=>F);

end behavioral;

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