5) Complete the hierarchical VHDL code below to implement the AOI circuit. The d

Question

5) Complete the hierarchical VHDL code below to implement the AOI circuit. The design consists of four design files. There is an AND design, INV design and OR design. Each design is implemented using a CASE statement to show various CASE configuration. int I AND GATE: hw11 p5_ and.vhd library IEEE; use IEEE STD LOGIC 1164 ALL: entity hw11 p5_and is Port (signal in1, in2: in STD LOGIC; signal out STD LOGIC); end hw11 p5 and; architecture behavioral of hw11 p5 and is begin process (in1, ) is begin case std logic vector(in1, in2) is when "11and out1, when others => and-out end case end process; end behavioral OR GATE: hw11 p5 or shd library EEE; use IEEE STD LOGIC 1164 ALL; entity hw11 p5_or is Port (signal in STD LOGIC; signal or out:out STD LOGIC) end hw11 p5 or; architecture behavioral of hw11 _pS_or is begin process (in1, in2) is begin case std logic_vector (in1, in2) is a list of cases to check separated by I when "01"I 10"I when others or out O or out 1 end case end process; end behavioral;

Explanation / Answer

I've given answers for each blank in a sequential manner

AND BLOCK : and_out , in2

OR BLOCK : in1, in2, "11"

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