In the following Verilog code, A , B , C , and D are bit signals that are \'0\'

Question

In the following Verilog code, A, B, C, and D are bit signals that are '0' at time = 4 ns. If A changes to 1 at time 5 ns, make a table showing the values of A, B, C, and D as a function of time until time = 18 ns. Include deltas. Indicate the times at which each always block begins executing.

      //P1

      always @ (A)

      begin

         #5;

         B <= A;

         #2;

         C <= #1 B;

      end

      //P2

      always @ (B)

      begin

         A <= ~B;

         D <= ~A ^ B;

      end

Explanation / Answer

At 0ns:A=0,B=0,C=0,D=0.

At 5ns(sampled values:A=0,B=0,C=0,D=0): A changes to 1:process P1 is triggered which schedules event B<=A at 10ns and C<=#1B at 12ns. Thus at 5ns:A=1,B=0,C=0,D=0.

At 10ns(sampled values:A=1,B=0,C=0,D=0): P1 B<=A is executes. Here A=1, thus B=1. This change in B triggers process P2 which schedules 2 events A<=B and D<=~A^B.At 10ns:A=1,B=1,C=0,D=0
At 10+delta ns(sampled values:A=1,B=1,C=0,D=0): P2 executes. Thus A=~B=0 and D=~A^B=0^1=1.
At 10+delta ns: A=0,B=1,C=0,D=1.(The change in value of A cannot start P1 again as previous P1 is not finished yet)

At 12ns(sampled values:A=0,B=1,C=0,D=1): Values remain same as C has to be updated after 1ns due to intra assignment delay.At 12ns:A=0,B=1,C=0,D=1.

At 13ns(sampled values:A=0,B=1,C=0,D=1): C=B=1. Thus at 13ns: A=0,B=1,C=1,D=1(here we come out of P1 process and start waiting for an event in A again, since this never happens, values don't change after this time).

At 18ns:A=0,B=1,C=1,D=1.

time(ns) A B C D 0 0 0 0 0 5 1 0 0 0 10 1 1 0 0 10+delta 0 1 0 1 12 0 1 0 1 13 0 1 1 1

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