A processor is capable of carrying out the following operations. Each micro-oper

Question

A processor is capable of carrying out the following operations. Each micro-operation takes one more operands. The operands represent register addresses, and the micro-operations are carried out on the contents of the registers as described below. Registers R1, R2, R3, and R4 have the following starting values: R1 = 00000000 R2 = 10011101 R3 = 10100101 R4 = 01100110. Suppose that the processor executes following sequence of micro-operations. In each case, the value of R1 that results from an instruction is the value of R1 at the next instruction uses. Show the contents of R1 after each step of the program. Remember that since R1 receives the result of each operation, that the R1 you find as the result the processor uses in the next step.

Explanation / Answer

1) BSET(R1,R2) -- initially R1 was 0 and R2 = 0x9B. So the microinstruction simply set the bits of R1 according to the bitmask pattern defined by R2, which results in R2 itself as R1 is all 0's.

2) CIL(R1) -- in circular left shifts, the MSB bit of the operand becomes the LSB and all other bits in the operand shifts left by one position.

3) BCMP(R1, R3) -- In this micro instruction, the certain bits in the operand gets complemented depending on the bitmask pattern.

4) ASR(R1)-- arithmetic right shift retains the sign bit, i.e D7, while D7-D1 is shifted right and D0 is discarded. This is useful for operations which require two's complement.

5) BCLR(R1,R4)-- this operation clears the certain bits of the operand as defined by the bit mask pattern. Internally, to clear the desired bits, bitwise AND operation is performed between the operand and the mask.

6) LSL(R1)-- logical left shift is simply multiplying the number by 2, by just shifting all the bits to left by one bit and padding the LSB with 0. In the process the previous MSB, D7 overflows.

MICRO-INSTRUCTION VALUE OF R1 BSET(R1,R2) R1=10011101 CIL(R1) R1=00111011 BCMP(R1, R3) R1=10011110 ASR(R1) R1=11001111 BCLR(R1,R4) R1=11001001 LSL(R1) R1=10010010

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