Modify Figure 10.16 (Verilog code for a 4-bit unsigned multiplier) in order to c

Question

Modify Figure 10.16 (Verilog code for a 4-bit unsigned multiplier) in order to create Verilog code for an 8bit unsigned multiplier

bit multiplier module Mul 4 (a b, p) input 13:0] a, b output 17 p form partial products wire [3 01 ppo wire 13 0 ppl a & (b [1] x2 wire 13 01 pp2 a & 4 b (21 x4 wire [3 0] pp3 sum up partial products wire cout 1 cout2, cout 3 wire [3 0] s1, s2, S 3 Adder (4) al (pp1, 11 bo, ppo [3 1]), 1' bo cout1, s1) Adder ft (4) a 2 (pp2, fcoutl, s1 [3 1] t, 1 bo, cout2, s2) Adder t (4) a3 (pp3 fcout2, s2 [3 1] l, 1 bo, cout s3) collect the result assign p (cout 3, s 3, s [o], s [o], ppo l01 l endmodule Figure 10.16. Verilog code for a four-bit unsigned multiplier

Explanation / Answer

// 8-bit multiplier
module Mul8(a,b,p);
   input [7:0] a,b;
   output [15:0] f;
  
   // partial products
  
   wire [7:0] pp0 = a & {8{b[0]}}; // x 1
   wire [7:0] pp1 = a & {8{b[1]}}; // x 2
   wire [7:0] pp2 = a & {8{b[2]}}; // x 3
   wire [7:0] pp3 = a & {8{b[3]}}; // x 4
   wire [7:0] pp4 = a & {8{b[4]}}; // x 5
   wire [7:0] pp5 = a & {8{b[5]}}; // x 6
   wire [7:0] pp6 = a & {8{b[6]}}; // x 7
   wire [7:0] pp7 = a & {8{b[7]}}; // x 8
  
  
   wire cout1,cout2,cout3,cout4,cout5,cout6,cout7;
  
   wire [7:0] s1,s2,s3,s4,s5,s6,s7;
  
   // Assumed that Adder1 #(8) will work as 8 bit paraller adder.
   Adder1 #(8) a1(pp1, {1'b0, pp0[7:1]}, 1'b0, cout1, s1);
   Adder1 #(8) a2(pp2, {cout1, s1[7:1]}, 1'b0, cout2, s2);
   Adder1 #(8) a3(pp3, {cout2, s2[7:1]}, 1'b0, cout3, s3);
   Adder1 #(8) a4(pp4, {cout3, s3[7:1]}, 1'b0, cout4, s4);
   Adder1 #(8) a5(pp5, {cout4, s4[7:1]}, 1'b0, cout5, s5);
   Adder1 #(8) a6(pp6, {cout5, s5[7:1]}, 1'b0, cout6, s6);
   Adder1 #(8) a7(pp7, {cout6, s6[7:1]}, 1'b0, cout7, s7);
  
   // Result
   assign p = {cout7, s7, s6[0] , s5[0], s4[0], s3[0], s2[0] , s1[0], pp0[0]};
  
endmodule

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