Figure 1: ADDERSUBTRACTOR. Procedure: 1. Open a project, call it TOP 2. open a n

Question

Figure 1: ADDERSUBTRACTOR. Procedure: 1. Open a project, call it TOP 2. open a new VHDL file then copy your addsub code below: LIBRARY ieee, use icee sad logic 1164 ALL: use ieee-std logic arith all use ieeeestd logic igned all ENTITY add sub IS in std logic vector(3 downto 0% in std logic vector(3 downto 0% in std logic. carry in: out std logic vector(3 downto o) out std logic carry out: END addsub ARCHITECTURE beh OF addsub IS signal result: std logic vector(4 downto 0) BEGIN PROCESS (carry in) BEGIN IF THEN

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity addsub is
Port ( a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
carry_in : in std_logic;
sum : out std_logic_vector(3 downto 0);
carry_out : out std_logic);
end fab;

architecture Behavioral of addsub is

begin
process(a,b,carry_in)
begin
if(a='0' and b='0' and carry_in='0')then
s<='0';
carry_out<='0';
elsif( a='0' and b='0' and carry_in='1')then
  s<='1';
carry_out<='0';
  elsif( a='0' and b='1' and carry_in='0')then
  s<='1';
carry_out<='0';
  elsif( a='0' and b='1' and carry_in='1')then
  s<='0';
carry_out<='1';
elsif( a='1' and b='0' and carry_in='0')then
  s<='1';
carry_out<='0';
   elsif( a='1' and b='0' and carry_in='1')then
  s<='0';
carry_out<='1';
   elsif( a='1' and b='1' and carry_in='0')then
  s<='0';
carry_out<='1';
else
s<='1';
carry_out<='1';
end if;
end process;

end Behavioral;

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