I am wondering how can I use \"Y1\" in the second architecture. I am trying to c

Question

I am wondering how can I use "Y1" in the second architecture. I am trying to create a sign full adder -------------------------------------------------------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY S_FA IS port(ADD,X,Y,C_IN :IN STD_LOGIC; Sum,C_OUT :OUT STD_LOGIC); End S_FA; architecture Comp OF S_FA Is SIGNAL Y1 : STD_LOGIC; begin Y1 <= (ADD XOR Y); End Comp; architecture logic_func OF S_FA Is begin Sum <= (X XOR Y1 XOR C_IN); C_OUT <= (X AND Y1) OR (C_IN AND X) OR (C_IN AND Y1); end logic_func;

Explanation / Answer

library ieee; use ieee.std_logic_1164.all; entity fullAdder_tb is end fullAdder_tb; architecture tb of fullAdder_tb is component fullAdder is port( A, B, Cin : in std_logic; sum, Cout : out std_logic); end component; signal A, B, Cin, sum, Cout : std_logic; begin mapping: fullAdder port map(A, B, Cin, sum, Cout); --concurrent processes process begin Cin

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