Design a synchronous counter using D - flip - flops: the counter should go throu

Question

Design a synchronous counter using D - flip - flops: the counter should go through the following sequence of states where letters A - F denote used states and the binary numbers denote state variables Q2Q1Q0 Complete the state table assuming don't cares for the unused states. Obtain the excitation equations for the flip - flop inputs. Draw the circuit diagram. Determine the next state for each of the unused states. Is it a self - correcting design? If not. modify the design to obtain a solution without banging states.

Explanation / Answer

  Present state      Next state                    D inputs Q2   Q1   Q0   Q2*   Q1*   Q0*      D2   D1   D0 0      0      0      d      d      d               d      d      d 0      0      1      0      1      1               0      1      1 0      1      0      1      1      0               1      1      0 0      1      1      0      1      0               0      1      0 1      0      0      1      0      1               1      0      1 1      0      1      0      0      1               0      0      1 1      1      0      1      0      0               1      0      0 1      1      1      d      d      d               d      d      d Excitation equations for the D inputs D2 = m( 2,4,6) and dontcare d=m(0,7) Simplifying D2 = Q0 ' D1 = m( 1,2,3) and dontcare d=m(0,7) Simplifying D1 = Q2 ' Simplifying D1 = Q2 ' D0 = m( 1,4,5) and dontcare d=m(0,7) Simplifying D0 = Q1 ' Implementing Sorry, there is some error in loading the logic diagram using custom drawing Here is how u can draw the logic diagram Let FF0, FF1, AND FF2 be three D flip flops D0 , D1 and D2 are the inputs of FF0, FF1 and FF2 respectively C0 , C1 and C2 are the clock inputs of FF0, FF1 and FF2 respectively Q0 , Q1 and Q2 are the normal outputs of FF0, FF1 and FF2 respectively Q0' , Q1' and Q2' are the complemented outputs of FF0, FF1 and FF2 respectively FF0 is the first FF representing the LSB FF1 is the second FF FF2 is the thrid FF representing the MSB Connect all the clock inputs togeth to from a single clock input for the counter Connect Q0' to D2 Connect Q1' to D0 Connect Q2' to D1 Simplifying D0 = Q1 ' Implementing Sorry, there is some error in loading the logic diagram using custom drawing Here is how u can draw the logic diagram Let FF0, FF1, AND FF2 be three D flip flops D0 , D1 and D2 are the inputs of FF0, FF1 and FF2 respectively C0 , C1 and C2 are the clock inputs of FF0, FF1 and FF2 respectively Q0 , Q1 and Q2 are the normal outputs of FF0, FF1 and FF2 respectively Q0' , Q1' and Q2' are the complemented outputs of FF0, FF1 and FF2 respectively FF0 is the first FF representing the LSB FF1 is the second FF FF2 is the thrid FF representing the MSB Connect all the clock inputs togeth to from a single clock input for the counter Connect Q0' to D2 Connect Q1' to D0 Connect Q2' to D1 C0 , C1 and C2 are the clock inputs of FF0, FF1 and FF2 respectively Q0 , Q1 and Q2 are the normal outputs of FF0, FF1 and FF2 respectively Q0 , Q1 and Q2 are the normal outputs of FF0, FF1 and FF2 respectively Q0' , Q1' and Q2' are the complemented outputs of FF0, FF1 and FF2 respectively Q0' , Q1' and Q2' are the complemented outputs of FF0, FF1 and FF2 respectively FF0 is the first FF representing the LSB FF1 is the second FF FF2 is the thrid FF representing the MSB Connect all the clock inputs togeth to from a single clock input for the counter Connect all the clock inputs togeth to from a single clock input for the counter Connect Q0' to D2 Connect Q1' to D0 Connect Q2' to D1     

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