Design the double-cascode current source Fig. P7.37 to provide I =0.1 mA and the

Question

Design the double-cascode current source Fig. P7.37 to provide I =0.1 mA and the largest possible signal at the output; that is, design for the minimum allowable voltage across each transistor. The 0.18- mu m CMOS fabrication process available has - 6 V/mu m, and . Use devices with L = 0.5 mu m, and . Specify V G1, V G2, V G3, and the WIL of the transistors. What is the value of Ro achieved? Figure P7.38 shows a folded-cascode CMOS amplifier a simple current source Q2, supplying a current 2l, a cascaded current-source (Q4, Q5) supplying a current l. Assume, for simplicity, that all transistor have equal parameter

Explanation / Answer

ID=1/2*p*Cox*W/L*VOV2==>W/L=2*0.0001/(0.0001/V2*0.22)=50

ro=VA/ID*L=(6*0.18)/0.0001=10800 ==>VG1=VDD-vtp-VOV=1.8-0.5-0.2=1.1 V

VG2=VD1max-Vtp-VOV=1.8-0.2-0.5-0.2=0.9 V==>VG3=VD2max-Vtp-VOV=

1.8-0.2-0.2-0.5-0.2=0.7 V==>R0gm2*r03=0.0012*108003=1259712 or

1.26 M

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