For your first project, you are required to design, implement, and test an 4-bit

Question

For your first project, you are required to design, implement, and test an 4-bit fulladder.
Recommended Design Procedure:

USING XILINX write the coding for:

1)Implement design using VHDL

2)force the input manually.

3)Test your design by creating a test bench

***Follow the pic bellow but for 4-bit adder:

Now can start programming in required level sign 1 |,|View:Implementation C View: (. E Implementation( JSimulation- Simulation 2 --Company: Engineer: 5 -- Create Date: 7Module Name: Hierarc Comparator xc3s100e-4cp132 17:01:30 08/21/2015 -- Design Name: Comparator1bit-Behavioral Comparatoribit - Behavioral 8 --Project Name: -- Target Devices: 10 Tool versions %) 11 -- Description: 12 %| 13 I 14 Dependencies: 15 -Revision: 16 17 18 19 20 library IEEE: 21 use IEEE. STD LOGIC 1164.ALL No Processes Running Revision 0.01-File Created Additional CommentS: No single design module is selected CIHy Design Utilities 23 -Uncomment the following 1ibrary declaration if using 24 -- arithmetic functions with Signed or Unsigned values 25 -use IEEE.NUMERIC STD.ALL 26 27 28 -Uncomment the following library declaration if instantiating any Xilinx primitives in this code -- StartDesignFiles Lit Comparator 1bit.vhd Design Summary ors

Explanation / Answer

4 BIT FULL ADDER:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder is
port (X,Y , Cin : in bit;Cout,Sum : out bit);
end FullAdder;
architecture Behavioral of FullAdder is begin
Sum <= X xor Y xor Cin after 10 ns;
Cout <= (X and Y ) or (X and Cin) or (Y and Cin) after 10 ns;
end Behavioral;
---------------------------------------------------------------------------------------------------------
and Here is the VHDL code for the Top Module 4 bit Adder
---------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Adder4 is
port (A,B : in bit_vector(3 downto 0); ----inputs Cin : in bit ;
S : out bit_vector(3 downto 0); ------Outputs
Co : out bit);
end Adder4;
architecture Behavioral of Adder4 is
component FullAdder
port (X,Y , Cin : in bit;
Cout,Sum : out bit);
end component;
signal C: bit_vector(3 downto 1);
begin---Instantiate four copies of the full adder
FA0: FullAdder port map (A(0),B(0),Cin,C(1),S(0));
FA1: FullAdder port map (A(1),B(1),C(1),C(2),S(1));
FA2: FullAdder port map (A(2),B(2),C(2),C(3),S(2));
FA3: FullAdder port map (A(3),B(3),C(3),Co,S(3));
end Behavioral;

>>>>VHDL FULL ADDER PROGRAM

>First we will design a Half Adder entity
>Second we will desgin a OR gate entity.
>Third we will combine those two entities to form a Full Adder.    

library ieee;
use ieee.std_logic_1164.all;
entity andGate is port( A, B : in std_logic;F : out std_logic);
end andGate;
architecture func of andGate is
begin
F <= A and B;
end func;
============================
Here we define the XOR gate that we need for the Half Adder
library ieee;
use ieee.std_logic_1164.all;
entity xorGate is
port(A, B : in std_logic;F : out std_logic);
end xorGate;
architecture func of xorGate is
begin
F <= A xor B;
end func;
============================
At this point we construct the half adder using the AND and XOR gates
library ieee;
use ieee.std_logic_1164.all;
entity halfAdder is
port( A, B : in std_logic;sum, Cout : out std_logic);
end halfAdder;
architecture halfAdder of halfAdder is component andGate is -- import AND Gate
port( A, B : in std_logic;F : out std_logic);
end component;
component xorGate is -- import XOR Gate
port( A, B : in std_logic;F : out std_logic);
end component;
begin
G1 : xorGate port map(A, B, sum);
G2 : andGate port map(A, B, Cout);
end halfAdder;
======================*=================== END HALF ADDER
Now we define the OR gate that we need for the Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity orGate is
port(A, B : in std_logic;F : out std_logic);
end orGate;
architecture func of orGate is
begin
F <= A or B;
end func;
==============================*
==============================*
We are finally ready to build the Full Adder
library ieee;
use ieee.std_logic_1164.all;
entity fullAdder is port( A, B, Cin : in std_logic;sum, Cout : out std_logic);
end fullAdder;
--
architecture fullAdder of fullAdder is
component halfAdder is --import Half Adder entity
port( A, B : in std_logic;sum, Cout : out std_logic);
end component;
component orGate is --import OR Gate entity
port( A, B : in std_logic;F : out std_logic);
end component;
signal halfTohalf, halfToOr1, halfToOr2: std_logic;
begin
G1: halfAdder port map(A, B, halfTohalf, halfToOr1);
G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2);
G3: orGate port map(halfToOr1, halfToOr2, Cout);
end fullAdder;

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