I am trying to put a clock divider into my VHDL code. I have two entities, one f
ID: 662843 • Letter: I
Question
I am trying to put a clock divider into my VHDL code. I have two entities, one for the clock divider and one for my main VHDL. I am not sure how to do the timing for my lab because the clock I have is a 24HZ and I am supposed to use a 1 HZ clock, so I need to put in a clock divider. Here is my Lab instructions and my following code:
LAB INSTRUCTIONS
Design a controller to operate two separate sets of three traffic light signals, one for each direction. The configuration is shown in Figure 5.5. Use eight LEDs as shown in Table 5.1 to represent the outputs. The Time in This State can be met in several ways. One method is to use a debounced switch as input, another to input a 1 Hz clock, another to use the internal 24 MHz clock, and a frequency division circuit to create a 1 Hz output.
MAIN VHDL CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TrafficLight3 is
port (
clk: in STD_LOGIC;
clr: in STD_LOGIC;
lights: out STD_LOGIC_VECTOR(5 downto 0));
end TrafficLight3;
ARCHITECTURE circuit of TrafficLight3 is
type state_type is (s0, s1, s2, s3,);
signal state: state_type;
signal count: integer range 0 to 5;
constant SEC5: integer := 5;
constant SEC1: integer:= 1;
begin
process(clk,clr)
begin
if clr = '1' then
state <= s0;
count <= 0;
elsif (clk'event and clk = '1') then
case state is
when s0 =>
if count < SEC5 then
state <= s0;
count <= count + 1;
else
state <= s1;
count <= 0;
end if;
when s1 =>
if count < SEC1 then
state <= s1;
count <= count + 1;
else
state <= s2;
<= 0;
end if;
when s2 =>
if count < SEC1 then
state <= s3;
count <= count + 1;
else
state <= s3;
count <= 0;
end if;
when s3 =>
if count < SEC5 then
state <= s3;
count <= count + 1;
else
state <= s0;
count <= 0;
end if;
when others => state <= s0;
end case;
end if;
end process;
C2: process (state)
begin
case state is
when s0 => lights <="100001";
when s1 => lights <= "100010";
when s2 => lights <= "100100";
when s3 => lights <= "001100";
when others => lights <= "100001";
end case;
end process;
end behavior;
CLOCK DIVDER VHDL
entity c1hz is
port( clk:in bit; clkout:out bit);
end c1hz;
architecture behavior of c1hz is
begin
process(clk)
variable cnt : integer range 0 to 12;
begin
if(clk'event and clk='1') then
if(cnt=12587500)then
cnt:=0;
clkout<='1';
else
cnt := cnt+1;
clkout<='0';
end if;
end if;
end process;
end behavior;
Explanation / Answer
Since you want to divide a 24MHz clock, i.e 24000000 Hz, to 1 Hz, you must create a counter that will count up every rising edge of the input clock (24 MHz). After 12000000 counts, you reach the mid point. Thereafter, change the level value of the output signal.
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