Make program using Verilog HDL. 6. You are to develop a state diagram for a wash

Question

Make program using Verilog HDL. 6. You are to develop a state diagram for a washing machine. The machine starts when a coin is deposited. It then sequences through the following stages: soak, wash, rinse, and spin. There is a double wash switch, which, if turned on, causes a second wash and rinse to occur. There is one timer-you may assume that each stage should take the same amount of time. The timer begins ticking as soon as the coin is deposited, generates a T signal at the end of the time period, and then resets itself and starts again. If the lid is raised during the spin cycle, the machine stops spinning until the lid is closed. You may assume that the timer suspends ticking while the lid is raised. Identify your inputs and outputs. and implements this finite state machine.

Explanation / Answer

Program:

module washmachine (rst, clk, start, w, s, a, m, d);

initial a=0;

initial m=0;

initial s=0;

initial d=0;

always@ (posedge clk, posedge rst)

begin

if (rst)

begin

state<= _initial;

end

else

begin

case (state)

_initial:

Fill:

Wash:

Drain:

Fill:

Rinse:

Drain:

Dry:

Default:

endcase

end

endmodule

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