LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Alu4 IS GENERIC(CONSTANT N: IN

ID: 644986 • Letter: L

Question

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Alu4 IS
GENERIC(CONSTANT N: INTEGER:=4;    --4 BITS ALU
          CONSTANT Z: STD_LOGIC_VECTOR(3 DOWNTO 1):="000" --3 ZEROs
          );
PORT(a,b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
       control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
       overflow: OUT STD_LOGIC;
       zero: OUT STD_LOGIC;
       carryOut: OUT STD_LOGIC;
       result: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
       );
       END Alu4;

ARCHITECTURE imp OF Alu4 IS
COMPONENT Alu1
PORT(a,b: IN STD_LOGIC;
      carryIn: IN STD_LOGIC;
      control: IN STD_LOGIC;
      result: OUT STD_LOGIC;
      carryOut: OUT STD_LOGIC;
      );
      END COMPONENT;
SIGNAL carry_sig: STD_LOGIC_VECTOR(N DOWNTO 0); --carry_sig(N) = MSB carryOut
SIGNAL result_sig: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
BEGIN

      --Dont understand where to begin and how to name my parameters.
      -- suppose to use generate ...port map
END imp;

if you need the 1bit alu, here it is

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY Alu1 IS
 PORT(a,b: IN STD_LOGIC;
 CarryIn: IN STD_LOGIC;
 control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
 result: OUT STD_LOGIC;
 carryOut: OUT STD_LOGIC
 );
END Alu1;

ARCHITECTURE imp OF Alu1 IS
COMPONENT Adder1
PORT(a,b: IN STD_LOGIC;
 cIn: IN STD_LOGIC;
 sum: OUT STD_LOGIC;
 cOut: OUT STD_LOGIC);
END COMPONENT;
SIGNAL a_sig, b_sig: STD_LOGIC;
SIGNAL sum_sig, carryOut_sig: STD_LOGIC;
SIGNAL result_sig: STD_LOGIC;

BEGIN
a_sig <= a;
b_sig <= NOT b WHEN control = "11" ELSE --SUBTRACT (1'S COMPLEMENT)
 b;
co: Adder1 PORT MAP(a_sig, b_sig, carryIn, sum_sig, carryOut_sig);

--ADD and SUBTRACT operations do the same thing(ADD).
WITH control SELECT
result_sig <=
 a AND b WHEN "00", --AND
 a OR b WHEN "01", --OR
 sum_sig WHEN "10", --ADD
 sum_sig WHEN "11"; --SUBTRACT

 result<= result_sig;
 --carryOut= "0" when AND or OR operations
 carryOut <= '0' WHEN control = "00" OR control="01" ELSE
 carryOut_sig;

END imp;

Problem Description You are required to create a 4-bit Arithmetic Logic Unit (ALU) in VHDL. ALU is a digital circuit that performs arithmetic and logical operations. The ALU logic block Diagram and its operations shown as following:

Explanation / Answer

i think you are looking for formatting the above...

hope this wil helps you..

<img alt="" src="//d2vlcm61l7u1fs.cloudfront.net/media%2F6db%2F6db78bb1-9c98-431a-b2f2-6b28234c3fec%2FphpXVSNIH.png" />You need to demonstrate logical operations (AND and OR) and arithmetic operations (Add, Subtract). This 4-bit ALU uses the toggle switches as the inputs (4-bit a, 4-bit b, and 2-bit control lines).
 
LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Alu4 IS
 GENERIC(CONSTANT N: INTEGER:=4;    --4 BITS ALU
           CONSTANT Z: STD_LOGIC_VECTOR(3 DOWNTO 1):="000" --3 ZEROs
           );
 PORT(a,b: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
        control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        overflow: OUT STD_LOGIC;
        zero: OUT STD_LOGIC;
        carryOut: OUT STD_LOGIC;
        result: OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)
        );
        END Alu4;
      
 ARCHITECTURE imp OF Alu4 IS
 COMPONENT Alu1
 PORT(a,b: IN STD_LOGIC;
       carryIn: IN STD_LOGIC;
       control: IN STD_LOGIC;
       result: OUT STD_LOGIC;
       carryOut: OUT STD_LOGIC;
       );
       END COMPONENT;
 SIGNAL carry_sig: STD_LOGIC_VECTOR(N DOWNTO 0); --carry_sig(N) = MSB carryOut
 SIGNAL result_sig: STD_LOGIC_VECTOR(N-1 DOWNTO 0);
 BEGIN
 
       --Dont understand where to begin and how to name my parameters.
       -- suppose to use generate ...port map
 END imp;
if you need the 1bit alu, here it is
LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Alu1 IS
    PORT(a,b: IN STD_LOGIC;
         CarryIn: IN STD_LOGIC;
         control: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
         result: OUT STD_LOGIC;
         carryOut: OUT STD_LOGIC
         );
 END Alu1;
       
 ARCHITECTURE imp OF Alu1 IS
 COMPONENT Adder1
 PORT(a,b: IN STD_LOGIC;
        cIn: IN STD_LOGIC;
        sum: OUT STD_LOGIC;
        cOut: OUT STD_LOGIC);
 END COMPONENT;
 SIGNAL a_sig, b_sig: STD_LOGIC;
 SIGNAL sum_sig, carryOut_sig: STD_LOGIC;
 SIGNAL result_sig: STD_LOGIC;
       
 BEGIN
 a_sig <= a;
 b_sig <= NOT b WHEN control = "11" ELSE       --SUBTRACT (1'S COMPLEMENT)
            b;
 co: Adder1 PORT MAP(a_sig, b_sig, carryIn, sum_sig, carryOut_sig);

           --ADD and SUBTRACT operations do the same thing(ADD).
 WITH control SELECT
 result_sig <=
    a AND b WHEN "00", --AND
     a OR b WHEN "01", --OR
     sum_sig WHEN "10", --ADD
    sum_sig WHEN "11"; --SUBTRACT
   
    result<= result_sig;
               --carryOut= "0" when AND or OR operations
    carryOut <= '0' WHEN control = "00" OR control="01" ELSE
                carryOut_sig;
                         
 END imp;

Navigate

LIBPB.C #include \"libpb.h\" #include <string.h> #include <stdio.h> void add_per

LIBRARY ieee; ----------------------- USE ieee.std_logic_1164.ALL; -- J-K FF --

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY Alu4 IS GENERIC(CONSTANT N: IN

Question

Explanation / Answer

Related Questions

Navigate