LIBRARY ieee; ----------------------- USE ieee.std_logic_1164.ALL; -- J-K FF --
ID: 3566072 • Letter: L
Question
LIBRARY ieee; -----------------------
USE ieee.std_logic_1164.ALL; -- J-K FF --
-----------------------
ENTITY ex10_14 IS
PORT(n_cp, j, k : IN std_logic;
q : BUFFER std_logic);
END ex10_14;
ARCHITECTURE arc OF ex10_14 IS
SIGNAL jk : std_logic_vector (1 DOWNTO 0);
BEGIN
jk<=j&k;
PROCESS (n_cp, j, k)
BEGIN
IF (n_cp'EVENT AND n_cp= '0') THEN --Neg edge trigger
CASE jk IS
WHEN "00" => q <= q; --Hold
WHEN "01" => q <= '0'; --Reset
WHEN "10" => q <= '1'; --Set
WHEN "11" => q <= NOT q; --Toggle
WHEN OTHERS => q <= q;
END CASE;
END IF;
END PROCESS;
END arc;
Explanation / Answer
modified parts are in bold format. take a look
LIBRARY ieee; -----------------------
USE ieee.std_logic_1164.ALL; -- J-K FF --
-----------------------
ENTITY ex10_14 IS
PORT(n_cp, j, k, n_set, n_clr : IN std_logic;
q : BUFFER std_logic);
END ex10_14;
ARCHITECTURE arc OF ex10_14 IS
SIGNAL jk : std_logic_vector (1 DOWNTO 0);
BEGIN
jk<=j&k;
PROCESS (n_cp, j, k,n_clr,n_set)
BEGIN
IF (n_clr='0' ) THEN q='0' ; // Asynchronous active low Reset
ELSE IF (n_set='0' ) THEN q='1' ; // Asynchronous active low Set
ELSE IF (n_cp'EVENT AND n_cp= '0') THEN --Neg edge trigger
CASE jk IS
WHEN "00" => q <= q; --Hold
WHEN "01" => q <= '0'; --Reset
WHEN "10" => q <= '1'; --Set
WHEN "11" => q <= NOT q; --Toggle
WHEN OTHERS => q <= q;
END CASE;
END IF;
END PROCESS;
END arc;
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