- MIPS five stage pipeline is given as IF Instruction fetch from memory ID Instr

Question

- MIPS five stage pipeline is given as IF Instruction fetch from memory ID Instruction decode and register read EX Execute operation or calculate address MEM: Access memory operand WB: Write result back to register Each of the following sequence of MIPS codes causes data hazards, assuming that forwarding is not allowed and NOP can be used only if instructions cannot be rearranged, Suggest a solution for each case - Case 1 Case 2 -Orginal code: and or add -Updated code: -Orginal code add $s5,Ss2, Ss1 lw $S3,4($s5) Iw 2, 0(Ss2) $s1, $s2, $s3 $s2, $s1, $s4 $s1, Ss1, Ss3 -Updated code: Draw updated program execution in five stage pipeline: Draw updated program execution in five stage pipeline No. of Cycles for updated codeNo. of Cycles for updated code / No. of cycles for original code - No. of cycles for original code-

Explanation / Answer

Case 1)

Updated Code:

add $s5,$s2,$s1

lw $s2,0($s2)

nop

nop

nop

lw $s3,4($s5)

In upadted code 10 cycle are required.

In original code: 7 cycles are required.

Note: If we use original code the cycle might be less but the result will be incorrect due to data dependency.

10/7=1.42

Case 2)

Here we cannot rearrange the code as all are dependent.

Updated Code:

and $s1,$s2,$s3

nop

nop

nop

nop

or $s2,$s1,$s4

add $s1,$s1,$3

In upadted code 11 cycle are required.

In original code: 7 cycles are required.

Note: If we use original code the cycle might be less but the result will be incorrect due to data dependency.

11/7=1.571

1 2 3 4 5 6 7 8 9 10 I1 IF ID EX MA WB I3 IF ID EX MA WB I2 N N N IF ID EX MA WB

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