1. Assume a 5-stage pipeline (IF, ID, EX, MEM, WB) with no bypassing. What stage
ID: 3903806 • Letter: 1
Question
1. Assume a 5-stage pipeline (IF, ID, EX, MEM, WB) with no bypassing.
What stage is instruction 2 at in the 5th instruction time slot? # i2_5
What stage is instruction 3 at in the 9th instruction time slot? # i3_9
If an instruction is not in any stage during a time slot cycle, select the option NA.
a. i2_5 is :_______________________ (IF, ID, EX, NA, MEM, WB)
b. I3_9 is :_______________________ (IF, ID, EX, NA, MEM, WB)
2.
Consider the following sequence of instructions in a MIPS 5-stage pipeline:
For the instruction mix shown above, on what instruction result does the last add instruction depend on?
add $4, $1, $2
lw $1, 0($4)
sub $1, $1, $1
beq $1, $2, ADD_LABEL
1 2 3 4 5 6 7 8 9 10 11 12 i1 i2 i2_5 i3 i3_9 i4Explanation / Answer
Answer is as follows :
Answer 1 :
According to given information the complete pipeline diagram with no bypassing is as follows :
* indicates stalls / bubbles in pipeline.
Bold letters in pipeline are answers of blanks , so
a. i2_5 is : ID
b. I3_9 is : EX
Answer 2 :
As we see in the given instructions the last instruction "add $1, $1, $1" uses the register $1 which is previously updated with it's previous instruction "sub $1, $1, $1". The result of last instruction is totally depend on this instruction.
So the correct answer is C i.e. sub $1, $1, $1
if there is any query please ask in comments...
1 2 3 4 5 6 7 8 9 10 11 12 13 14 i1 IF ID EX MEM WB i2 IF * * ID EX MEM WB i3 IF * * ID EX MEM WB i4 IF * * ID EX MEM WBRelated Questions
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